test_double3.tan.qmsg

DDS锯齿波发生器： 开发平台：maxplus＋FPGA 功能： 输出X路扫屏锯齿波。频率可用键盘精确控制

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 20 15:13:09 2005 " "Info: Processing started: Sat Aug 20 15:13:09 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off test_double3 -c test_double3 --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off test_double3 -c test_double3 --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node CLK is an undefined clock" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" "" "" { Schematic "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" { { 96 88 256 112 "CLK" "" } { 88 256 312 104 "CLK" "" } { 224 1024 1048 240 "CLK" "" } { 400 328 368 416 "CLK" "" } } } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ALE " "Info: Assuming node ALE is an undefined clock" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" "" "" { Schematic "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" { { 360 104 272 376 "ALE" "" } } } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "ALE" } } } }  } 0}  } {  } 0}