test_double3.fit.qmsg

DDS锯齿波发生器： 开发平台：maxplus＋FPGA 功能： 输出X路扫屏锯齿波。频率可用键盘精确控制

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 20 15:12:58 2005 " "Info: Processing started: Sat Aug 20 15:12:58 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off test_double3 -c test_double3 " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off test_double3 -c test_double3" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "test_double3 EP1C3T144C8 " "Info: Selected device EP1C3T144C8 for design test_double3" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Info: Fitter is performing a Standard Fit compilation -- maximum Fitter effort will be used to optimize design performance" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6T144C8 " "Info: Device EP1C6T144C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CLK Global clock in PIN 16 " "Info: Automatically promoted signal CLK to use Global clock in PIN 16" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" "" "" { Schematic "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" { { 96 88 256 112 "CLK" "" } { 88 256 312 104 "CLK" "" } { 224 1024 1048 240 "CLK" "" } { 400 328 368 416 "CLK" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "FREDEVIDER8:inst8\|CLK Global clock " "Info: Automatically promoted some destinations of signal FREDEVIDER8:inst8\|CLK to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREDEVIDER8:inst8\|CLK " "Info: Destination FREDEVIDER8:inst8\|CLK may be non-global or may not use global clock" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/FREDEVIDER8.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/FREDEVIDER8.vhd" 17 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "generator_add:inst4\|add~47 " "Info: Destination generator_add:inst4\|add~47 may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "generator_add:inst4\|add~48 " "Info: Destination generator_add:inst4\|add~48 may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "generator_add:inst4\|add~49 " "Info: Destination generator_add:inst4\|add~49 may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "generator_add:inst4\|add~50 " "Info: Destination generator_add:inst4\|add~50 may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "generator_add:inst4\|add~51 " "Info: Destination generator_add:inst4\|add~51 may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "generator_add:inst4\|add~52 " "Info: Destination generator_add:inst4\|add~52 may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "generator_add:inst4\|add~53 " "Info: Destination generator_add:inst4\|add~53 may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "generator_add:inst4\|add~54 " "Info: Destination generator_add:inst4\|add~54 may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "generator_add:inst4\|add~55 " "Info: Destination generator_add:inst4\|add~55 may be non-global or may not use global clock" {  } {  } 0}  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/FREDEVIDER8.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/FREDEVIDER8.vhd" 17 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "ALE Global clock " "Info: Automatically promoted signal ALE to use Global clock" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" "" "" { Schematic "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" { { 360 104 272 376 "ALE" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "ALE " "Info: Pin ALE drives global clock, but is not placed in a dedicated clock pin position" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" "" "" { Schematic "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.bdf" { { 360 104 272 376 "ALE" "" } } } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "ALE" } } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" "" "" { Report "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3_cmp.qrpt" Compiler "test_double3" "UNKNOWN" "V1" "G:/ywh/QUARTUSII/sinWAVEgenerator/db/test_double3.quartus_db" { Floorplan "" "" "" { ALE } "NODE_NAME" } } } { "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.fld" "" "" { Floorplan "G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.fld" "" "" { ALE } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "BUS_51:inst9\|TMP Global clock " "Info: Automatically promoted some destinations of signal BUS_51:inst9\|TMP to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "BUS_51:inst9\|TMP " "Info: Destination BUS_51:inst9\|TMP may be non-global or may not use global clock" {  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" 53 -1 0 } }  } 0}  } { { "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" "" "" { Text "G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd" 53 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Start DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Completed DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_LUT_IO_MAC_RAM_PACKING" "" "Info: Moving registers into I/Os, LUTs, DSP and RAM blocks to improve timing and density" {  } {  } 0}