test_double3.hif

DDS锯齿波发生器： 开发平台：maxplus＋FPGA 功能： 输出X路扫屏锯齿波。频率可用键盘精确控制

Version 4.1 Build 181 06/29/2004 SJ Full Version
31
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# entity
lpm_bustri
# case_insensitive
# source_file
d:|altera|quartus41|libraries|megafunctions|LPM_BUSTRI.tdf
1088009428
6
# storage
db|test_double3.(2).cnf
db|test_double3.(2).cnf
# user_parameter {
LPM_WIDTH
8
PARAMETER_UNKNOWN
USR
}
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
enabledt
enabletr
result0
result1
result2
result3
result4
result5
result6
result7
tridata0
tridata1
tridata2
tridata3
tridata4
tridata5
tridata6
tridata7
}
# end
# entity
generator_reg81
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
generator_reg81.vhd
1124066220
4
# storage
db|test_double3.(3).cnf
db|test_double3.(3).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
FREDEVIDER8
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
FREDEVIDER8.vhd
1124065860
4
# storage
db|test_double3.(4).cnf
db|test_double3.(4).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
lpm_rom
# case_insensitive
# source_file
d:|altera|quartus41|libraries|megafunctions|LPM_ROM.tdf
1088009432
6
# storage
db|test_double3.(5).cnf
db|test_double3.(5).cnf
# user_parameter {
LPM_WIDTH
8
PARAMETER_UNKNOWN
USR
LPM_WIDTHAD
9
PARAMETER_UNKNOWN
USR
LPM_NUMWORDS
512
PARAMETER_UNKNOWN
USR
LPM_ADDRESS_CONTROL
REGISTERED
PARAMETER_UNKNOWN
DEF
LPM_OUTDATA
UNREGISTERED
PARAMETER_UNKNOWN
USR
LPM_FILE
e:\ywh\maxplus\fpga\sinwavegenerator\sin512.mif
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
address0
address1
address2
address3
address4
address5
address6
address7
address8
inclock
q0
q1
q2
q3
q4
q5
q6
q7
}
# include_file {
d:|altera|quartus41|libraries|megafunctions|altrom.inc
1081477590
d:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
}
# end
# entity
altrom
# case_insensitive
# source_file
d:|altera|quartus41|libraries|megafunctions|altrom.tdf
1088009418
6
# storage
db|test_double3.(6).cnf
db|test_double3.(6).cnf
# user_parameter {
WIDTH
8
PARAMETER_UNKNOWN
USR
AD_WIDTH
9
PARAMETER_UNKNOWN
USR
NUMWORDS
512
PARAMETER_UNKNOWN
USR
FILE
e:\ywh\maxplus\fpga\sinwavegenerator\sin512.mif
PARAMETER_UNKNOWN
USR
REGISTERINPUTMODE
ADDRESS_CONTROL
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
2048
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
SUPPRESS_MEMORY_CONVERSION_WARNINGS
OFF
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
address0
address1
address2
address3
address4
address5
address6
address7
address8
clocki
q0
q1
q2
q3
q4
q5
q6
q7
}
# include_file {
d:|altera|quartus41|libraries|others|maxplus2|memmodes.inc
1081480922
d:|altera|quartus41|libraries|megafunctions|lpm_decode.inc
1081478592
d:|altera|quartus41|libraries|megafunctions|lpm_mux.inc
1081478758
d:|altera|quartus41|libraries|megafunctions|altqpram.inc
1081477546
d:|altera|quartus41|libraries|megafunctions|altsyncram.inc
1081477654
d:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
}
# end
# entity
altsyncram
# case_insensitive
# source_file
d:|altera|quartus41|libraries|megafunctions|altsyncram.tdf
1088009418
6
# storage
db|test_double3.(7).cnf
db|test_double3.(7).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_UNKNOWN
USR
WIDTHAD_A
9
PARAMETER_UNKNOWN
USR
NUMWORDS_A
512
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
e:\ywh\maxplus\fpga\sinwavegenerator\sin512.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_dcq
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
}
# include_file {
d:|altera|quartus41|libraries|megafunctions|stratix_ram_block.inc
1081479498
d:|altera|quartus41|libraries|megafunctions|lpm_mux.inc
1081478758
d:|altera|quartus41|libraries|megafunctions|lpm_decode.inc
1081478592
d:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
d:|altera|quartus41|libraries|megafunctions|altsyncram.inc
1081477654
d:|altera|quartus41|libraries|megafunctions|a_rdenreg.inc
1081476578
d:|altera|quartus41|libraries|megafunctions|altrom.inc
1081477590
d:|altera|quartus41|libraries|megafunctions|altram.inc
1081477560
d:|altera|quartus41|libraries|megafunctions|altdpram.inc
1081477328
d:|altera|quartus41|libraries|megafunctions|altqpram.inc
1081477546
}
# end
# entity
MUX2S
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
mux2s.vhd
1124066220
4
# storage
db|test_double3.(9).cnf
db|test_double3.(9).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
generator_add
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
generator_add.vhd
1124066040
4
# storage
db|test_double3.(10).cnf
db|test_double3.(10).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
generator_accB
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
generator_accb.vhd
1124066160
4
# storage
db|test_double3.(11).cnf
db|test_double3.(11).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
generator_reg82
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
generator_reg82.vhd
1124066220
4
# storage
db|test_double3.(12).cnf
db|test_double3.(12).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
lpm_counter
# case_insensitive
# source_file