test_double3.fit.eqn

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--G1_TEMP_Q_1[7] is generator_reg81:inst6|TEMP_Q_1[7] at LC_X12_Y2_N2
--operation mode is normal

G1_TEMP_Q_1[7]_sload_eqn = M1_q_a[7];
G1_TEMP_Q_1[7] = DFFEA(G1_TEMP_Q_1[7]_sload_eqn, GLOBAL(J1_CLK), !GLOBAL(K1_TMP), , , , );


--G1_TEMP_Q_1[6] is generator_reg81:inst6|TEMP_Q_1[6] at LC_X12_Y2_N5
--operation mode is normal

G1_TEMP_Q_1[6]_lut_out = M1_q_a[6];
G1_TEMP_Q_1[6] = DFFEA(G1_TEMP_Q_1[6]_lut_out, GLOBAL(J1_CLK), !GLOBAL(K1_TMP), , , , );


--G1_TEMP_Q_1[5] is generator_reg81:inst6|TEMP_Q_1[5] at LC_X11_Y2_N2
--operation mode is normal

G1_TEMP_Q_1[5]_sload_eqn = M1_q_a[5];
G1_TEMP_Q_1[5] = DFFEA(G1_TEMP_Q_1[5]_sload_eqn, GLOBAL(J1_CLK), !GLOBAL(K1_TMP), , , , );


--G1_TEMP_Q_1[4] is generator_reg81:inst6|TEMP_Q_1[4] at LC_X12_Y1_N4
--operation mode is normal

G1_TEMP_Q_1[4]_lut_out = M1_q_a[4];
G1_TEMP_Q_1[4] = DFFEA(G1_TEMP_Q_1[4]_lut_out, GLOBAL(J1_CLK), !GLOBAL(K1_TMP), , , , );


--G1_TEMP_Q_1[3] is generator_reg81:inst6|TEMP_Q_1[3] at LC_X12_Y1_N5
--operation mode is normal

G1_TEMP_Q_1[3]_sload_eqn = M1_q_a[3];
G1_TEMP_Q_1[3] = DFFEA(G1_TEMP_Q_1[3]_sload_eqn, GLOBAL(J1_CLK), !GLOBAL(K1_TMP), , , , );


--G1_TEMP_Q_1[2] is generator_reg81:inst6|TEMP_Q_1[2] at LC_X12_Y1_N2
--operation mode is normal

G1_TEMP_Q_1[2]_lut_out = M1_q_a[2];
G1_TEMP_Q_1[2] = DFFEA(G1_TEMP_Q_1[2]_lut_out, GLOBAL(J1_CLK), !GLOBAL(K1_TMP), , , , );


--G1_TEMP_Q_1[1] is generator_reg81:inst6|TEMP_Q_1[1] at LC_X12_Y2_N6
--operation mode is normal

G1_TEMP_Q_1[1]_lut_out = M1_q_a[1];
G1_TEMP_Q_1[1] = DFFEA(G1_TEMP_Q_1[1]_lut_out, GLOBAL(J1_CLK), !GLOBAL(K1_TMP), , , , );


--G1_TEMP_Q_1[0] is generator_reg81:inst6|TEMP_Q_1[0] at LC_X12_Y1_N6
--operation mode is normal

G1_TEMP_Q_1[0]_lut_out = M1_q_a[0];
G1_TEMP_Q_1[0] = DFFEA(G1_TEMP_Q_1[0]_lut_out, GLOBAL(J1_CLK), !GLOBAL(K1_TMP), , , , );


--H1_TEMP_Q_1[7] is generator_reg82:inst7|TEMP_Q_1[7] at LC_X15_Y2_N2
--operation mode is normal

H1_TEMP_Q_1[7]_sload_eqn = M1_q_a[7];
H1_TEMP_Q_1[7] = DFFEA(H1_TEMP_Q_1[7]_sload_eqn, !GLOBAL(J1_CLK), !GLOBAL(K1_TMP), , , , );


--H1_TEMP_Q_1[6] is generator_reg82:inst7|TEMP_Q_1[6] at LC_X15_Y2_N4
--operation mode is normal

H1_TEMP_Q_1[6]_sload_eqn = M1_q_a[6];
H1_TEMP_Q_1[6] = DFFEA(H1_TEMP_Q_1[6]_sload_eqn, !GLOBAL(J1_CLK), !GLOBAL(K1_TMP), , , , );


--H1_TEMP_Q_1[5] is generator_reg82:inst7|TEMP_Q_1[5] at LC_X15_Y2_N5
--operation mode is normal

H1_TEMP_Q_1[5]_sload_eqn = M1_q_a[5];
H1_TEMP_Q_1[5] = DFFEA(H1_TEMP_Q_1[5]_sload_eqn, !GLOBAL(J1_CLK), !GLOBAL(K1_TMP), , , , );


--H1_TEMP_Q_1[4] is generator_reg82:inst7|TEMP_Q_1[4] at LC_X15_Y1_N4
--operation mode is normal

H1_TEMP_Q_1[4]_lut_out = M1_q_a[4];
H1_TEMP_Q_1[4] = DFFEA(H1_TEMP_Q_1[4]_lut_out, !GLOBAL(J1_CLK), !GLOBAL(K1_TMP), , , , );


--H1_TEMP_Q_1[3] is generator_reg82:inst7|TEMP_Q_1[3] at LC_X15_Y1_N5
--operation mode is normal

H1_TEMP_Q_1[3]_sload_eqn = M1_q_a[3];
H1_TEMP_Q_1[3] = DFFEA(H1_TEMP_Q_1[3]_sload_eqn, !GLOBAL(J1_CLK), !GLOBAL(K1_TMP), , , , );


--H1_TEMP_Q_1[2] is generator_reg82:inst7|TEMP_Q_1[2] at LC_X15_Y1_N6
--operation mode is normal

H1_TEMP_Q_1[2]_sload_eqn = M1_q_a[2];
H1_TEMP_Q_1[2] = DFFEA(H1_TEMP_Q_1[2]_sload_eqn, !GLOBAL(J1_CLK), !GLOBAL(K1_TMP), , , , );


--H1_TEMP_Q_1[1] is generator_reg82:inst7|TEMP_Q_1[1] at LC_X12_Y2_N4
--operation mode is normal

H1_TEMP_Q_1[1]_lut_out = M1_q_a[1];
H1_TEMP_Q_1[1] = DFFEA(H1_TEMP_Q_1[1]_lut_out, !GLOBAL(J1_CLK), !GLOBAL(K1_TMP), , , , );


--H1_TEMP_Q_1[0] is generator_reg82:inst7|TEMP_Q_1[0] at LC_X15_Y1_N2
--operation mode is normal

H1_TEMP_Q_1[0]_lut_out = M1_q_a[0];
H1_TEMP_Q_1[0] = DFFEA(H1_TEMP_Q_1[0]_lut_out, !GLOBAL(J1_CLK), !GLOBAL(K1_TMP), , , , );


--M1_q_a[7] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[7] at M4K_X13_Y4
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 8
--Port A Logical Depth: 512, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
M1_q_a[7]_PORT_A_address = BUS(E1L43, E1L53, E1L63, E1L73, E1L83, E1L93, E1L04, E1L14, E1L24);
M1_q_a[7]_PORT_A_address_reg = DFFE(M1_q_a[7]_PORT_A_address, M1_q_a[7]_clock_0, , , );
M1_q_a[7]_clock_0 = GLOBAL(CLK);
M1_q_a[7]_PORT_A_data_out = MEMORY(, , M1_q_a[7]_PORT_A_address_reg, , , , , , M1_q_a[7]_clock_0, , , , , );
M1_q_a[7]_PORT_A_data_out_reg = DFFE(M1_q_a[7]_PORT_A_data_out, M1_q_a[7]_clock_0, , , );
M1_q_a[7] = M1_q_a[7]_PORT_A_data_out_reg[0];

--M1_q_a[0] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[0] at M4K_X13_Y4
M1_q_a[7]_PORT_A_address = BUS(E1L43, E1L53, E1L63, E1L73, E1L83, E1L93, E1L04, E1L14, E1L24);
M1_q_a[7]_PORT_A_address_reg = DFFE(M1_q_a[7]_PORT_A_address, M1_q_a[7]_clock_0, , , );
M1_q_a[7]_clock_0 = GLOBAL(CLK);
M1_q_a[7]_PORT_A_data_out = MEMORY(, , M1_q_a[7]_PORT_A_address_reg, , , , , , M1_q_a[7]_clock_0, , , , , );
M1_q_a[7]_PORT_A_data_out_reg = DFFE(M1_q_a[7]_PORT_A_data_out, M1_q_a[7]_clock_0, , , );
M1_q_a[0] = M1_q_a[7]_PORT_A_data_out_reg[7];

--M1_q_a[1] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[1] at M4K_X13_Y4
M1_q_a[7]_PORT_A_address = BUS(E1L43, E1L53, E1L63, E1L73, E1L83, E1L93, E1L04, E1L14, E1L24);
M1_q_a[7]_PORT_A_address_reg = DFFE(M1_q_a[7]_PORT_A_address, M1_q_a[7]_clock_0, , , );
M1_q_a[7]_clock_0 = GLOBAL(CLK);
M1_q_a[7]_PORT_A_data_out = MEMORY(, , M1_q_a[7]_PORT_A_address_reg, , , , , , M1_q_a[7]_clock_0, , , , , );
M1_q_a[7]_PORT_A_data_out_reg = DFFE(M1_q_a[7]_PORT_A_data_out, M1_q_a[7]_clock_0, , , );
M1_q_a[1] = M1_q_a[7]_PORT_A_data_out_reg[6];

--M1_q_a[2] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[2] at M4K_X13_Y4
M1_q_a[7]_PORT_A_address = BUS(E1L43, E1L53, E1L63, E1L73, E1L83, E1L93, E1L04, E1L14, E1L24);
M1_q_a[7]_PORT_A_address_reg = DFFE(M1_q_a[7]_PORT_A_address, M1_q_a[7]_clock_0, , , );
M1_q_a[7]_clock_0 = GLOBAL(CLK);
M1_q_a[7]_PORT_A_data_out = MEMORY(, , M1_q_a[7]_PORT_A_address_reg, , , , , , M1_q_a[7]_clock_0, , , , , );
M1_q_a[7]_PORT_A_data_out_reg = DFFE(M1_q_a[7]_PORT_A_data_out, M1_q_a[7]_clock_0, , , );
M1_q_a[2] = M1_q_a[7]_PORT_A_data_out_reg[5];

--M1_q_a[3] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[3] at M4K_X13_Y4
M1_q_a[7]_PORT_A_address = BUS(E1L43, E1L53, E1L63, E1L73, E1L83, E1L93, E1L04, E1L14, E1L24);
M1_q_a[7]_PORT_A_address_reg = DFFE(M1_q_a[7]_PORT_A_address, M1_q_a[7]_clock_0, , , );
M1_q_a[7]_clock_0 = GLOBAL(CLK);
M1_q_a[7]_PORT_A_data_out = MEMORY(, , M1_q_a[7]_PORT_A_address_reg, , , , , , M1_q_a[7]_clock_0, , , , , );
M1_q_a[7]_PORT_A_data_out_reg = DFFE(M1_q_a[7]_PORT_A_data_out, M1_q_a[7]_clock_0, , , );
M1_q_a[3] = M1_q_a[7]_PORT_A_data_out_reg[4];

--M1_q_a[4] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[4] at M4K_X13_Y4
M1_q_a[7]_PORT_A_address = BUS(E1L43, E1L53, E1L63, E1L73, E1L83, E1L93, E1L04, E1L14, E1L24);
M1_q_a[7]_PORT_A_address_reg = DFFE(M1_q_a[7]_PORT_A_address, M1_q_a[7]_clock_0, , , );
M1_q_a[7]_clock_0 = GLOBAL(CLK);
M1_q_a[7]_PORT_A_data_out = MEMORY(, , M1_q_a[7]_PORT_A_address_reg, , , , , , M1_q_a[7]_clock_0, , , , , );
M1_q_a[7]_PORT_A_data_out_reg = DFFE(M1_q_a[7]_PORT_A_data_out, M1_q_a[7]_clock_0, , , );
M1_q_a[4] = M1_q_a[7]_PORT_A_data_out_reg[3];

--M1_q_a[5] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[5] at M4K_X13_Y4
M1_q_a[7]_PORT_A_address = BUS(E1L43, E1L53, E1L63, E1L73, E1L83, E1L93, E1L04, E1L14, E1L24);
M1_q_a[7]_PORT_A_address_reg = DFFE(M1_q_a[7]_PORT_A_address, M1_q_a[7]_clock_0, , , );
M1_q_a[7]_clock_0 = GLOBAL(CLK);
M1_q_a[7]_PORT_A_data_out = MEMORY(, , M1_q_a[7]_PORT_A_address_reg, , , , , , M1_q_a[7]_clock_0, , , , , );
M1_q_a[7]_PORT_A_data_out_reg = DFFE(M1_q_a[7]_PORT_A_data_out, M1_q_a[7]_clock_0, , , );
M1_q_a[5] = M1_q_a[7]_PORT_A_data_out_reg[2];

--M1_q_a[6] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[6] at M4K_X13_Y4
M1_q_a[7]_PORT_A_address = BUS(E1L43, E1L53, E1L63, E1L73, E1L83, E1L93, E1L04, E1L14, E1L24);
M1_q_a[7]_PORT_A_address_reg = DFFE(M1_q_a[7]_PORT_A_address, M1_q_a[7]_clock_0, , , );
M1_q_a[7]_clock_0 = GLOBAL(CLK);
M1_q_a[7]_PORT_A_data_out = MEMORY(, , M1_q_a[7]_PORT_A_address_reg, , , , , , M1_q_a[7]_clock_0, , , , , );
M1_q_a[7]_PORT_A_data_out_reg = DFFE(M1_q_a[7]_PORT_A_data_out, M1_q_a[7]_clock_0, , , );
M1_q_a[6] = M1_q_a[7]_PORT_A_data_out_reg[1];


--J1_CLK is FREDEVIDER8:inst8|CLK at LC_X8_Y6_N2
--operation mode is normal

J1_CLK_lut_out = !J1_CLK;
J1_CLK = DFFEA(J1_CLK_lut_out, GLOBAL(CLK), VCC, , J1L2, , );


--K1_TMP is BUS_51:inst9|TMP at LC_X16_Y4_N5
--operation mode is normal

K1_TMP_lut_out = K1_LATCH_ADDRES[2] & !K1L06 & (K1_TMP # !K1L85) # !K1_LATCH_ADDRES[2] & (K1_TMP # !K1L85);
K1_TMP = DFFEA(K1_TMP_lut_out, !GLOBAL(CLK), VCC, , K1L12, , );


--E1L1 is generator_add:inst4|add~2 at LC_X19_Y4_N0
--operation mode is arithmetic

E1L1 = D1_REG_Q[7] $ K1_RAMTMP3[7];

--E1L3 is generator_add:inst4|add~2COUT0 at LC_X19_Y4_N0
--operation mode is arithmetic

E1L3_cout_0 = D1_REG_Q[7] & K1_RAMTMP3[7];
E1L3 = CARRY(E1L3_cout_0);

--E1L4 is generator_add:inst4|add~2COUT1 at LC_X19_Y4_N0
--operation mode is arithmetic

E1L4_cout_1 = D1_REG_Q[7] & K1_RAMTMP3[7];
E1L4 = CARRY(E1L4_cout_1);


--D1_REG_Q[7] is generator_accB:inst3|REG_Q[7] at LC_X18_Y5_N9
--operation mode is arithmetic

D1_REG_Q[7]_carry_eqn = (!D1L11 & D1L62) # (D1L11 & D1L72);
D1_REG_Q[7]_lut_out = D1_REG_Q[7] $ K1_RAMTMP1[7] $ D1_REG_Q[7]_carry_eqn;
D1_REG_Q[7] = DFFEA(D1_REG_Q[7]_lut_out, GLOBAL(J1_CLK), !GLOBAL(K1_TMP), , , , );

--D1L92 is generator_accB:inst3|REG_Q[7]~COUT at LC_X18_Y5_N9
--operation mode is arithmetic

D1L92 = CARRY(D1_REG_Q[7] & !K1_RAMTMP1[7] & !D1L72 # !D1_REG_Q[7] & (!D1L72 # !K1_RAMTMP1[7]));


--E1L43 is generator_add:inst4|add~47 at LC_X17_Y4_N2
--operation mode is normal

E1L43 = J1_CLK & E1L1 # !J1_CLK & D1_REG_Q[7];


--E1L5 is generator_add:inst4|add~3 at LC_X19_Y4_N1
--operation mode is arithmetic

E1L5 = D1_REG_Q[8] $ K1_RAMTMP2[0] $ E1L3;

--E1L7 is generator_add:inst4|add~3COUT0 at LC_X19_Y4_N1
--operation mode is arithmetic

E1L7_cout_0 = D1_REG_Q[8] & !K1_RAMTMP2[0] & !E1L3 # !D1_REG_Q[8] & (!E1L3 # !K1_RAMTMP2[0]);
E1L7 = CARRY(E1L7_cout_0);

--E1L8 is generator_add:inst4|add~3COUT1 at LC_X19_Y4_N1
--operation mode is arithmetic

E1L8_cout_1 = D1_REG_Q[8] & !K1_RAMTMP2[0] & !E1L4 # !D1_REG_Q[8] & (!E1L4 # !K1_RAMTMP2[0]);
E1L8 = CARRY(E1L8_cout_1);


--D1_REG_Q[8] is generator_accB:inst3|REG_Q[8] at LC_X18_Y4_N0
--operation mode is arithmetic

D1_REG_Q[8]_carry_eqn = D1L92;
D1_REG_Q[8]_lut_out = K1_RAMTMP0[0] $ D1_REG_Q[8] $ !D1_REG_Q[8]_carry_eqn;
D1_REG_Q[8] = DFFEA(D1_REG_Q[8]_lut_out, GLOBAL(J1_CLK), !GLOBAL(K1_TMP), , , , );

--D1L23 is generator_accB:inst3|REG_Q[8]~COUT0 at LC_X18_Y4_N0
--operation mode is arithmetic

D1L23_cout_0 = K1_RAMTMP0[0] & (D1_REG_Q[8] # !D1L92) # !K1_RAMTMP0[0] & D1_REG_Q[8] & !D1L92;
D1L23 = CARRY(D1L23_cout_0);

--D1L33 is generator_accB:inst3|REG_Q[8]~COUT1 at LC_X18_Y4_N0
--operation mode is arithmetic

D1L33_cout_1 = K1_RAMTMP0[0] & (D1_REG_Q[8] # !D1L92) # !K1_RAMTMP0[0] & D1_REG_Q[8] & !D1L92;
D1L33 = CARRY(D1L33_cout_1);


--E1L53 is generator_add:inst4|add~48 at LC_X15_Y4_N5
--operation mode is normal

E1L53 = J1_CLK & E1L5 # !J1_CLK & D1_REG_Q[8];


--E1L9 is generator_add:inst4|add~4 at LC_X19_Y4_N2
--operation mode is arithmetic

E1L9 = D1_REG_Q[9] $ K1_RAMTMP2[1] $ !E1L7;

--E1L11 is generator_add:inst4|add~4COUT0 at LC_X19_Y4_N2
--operation mode is arithmetic

E1L11_cout_0 = D1_REG_Q[9] & (K1_RAMTMP2[1] # !E1L7) # !D1_REG_Q[9] & K1_RAMTMP2[1] & !E1L7;
E1L11 = CARRY(E1L11_cout_0);

--E1L21 is generator_add:inst4|add~4COUT1 at LC_X19_Y4_N2
--operation mode is arithmetic

E1L21_cout_1 = D1_REG_Q[9] & (K1_RAMTMP2[1] # !E1L8) # !D1_REG_Q[9] & K1_RAMTMP2[1] & !E1L8;
E1L21 = CARRY(E1L21_cout_1);


--D1_REG_Q[9] is generator_accB:inst3|REG_Q[9] at LC_X18_Y4_N1
--operation mode is arithmetic

D1_REG_Q[9]_carry_eqn = (!D1L92 & D1L23) # (D1L92 & D1L33);
D1_REG_Q[9]_lut_out = D1_REG_Q[9] $ K1_RAMTMP0[1] $ D1_REG_Q[9]_carry_eqn;
D1_REG_Q[9] = DFFEA(D1_REG_Q[9]_lut_out, GLOBAL(J1_CLK), !GLOBAL(K1_TMP), , , , );

--D1L63 is generator_accB:inst3|REG_Q[9]~COUT0 at LC_X18_Y4_N1
--operation mode is arithmetic

D1L63_cout_0 = D1_REG_Q[9] & !K1_RAMTMP0[1] & !D1L23 # !D1_REG_Q[9] & (!D1L23 # !K1_RAMTMP0[1]);
D1L63 = CARRY(D1L63_cout_0);

--D1L73 is generator_accB:inst3|REG_Q[9]~COUT1 at LC_X18_Y4_N1
--operation mode is arithmetic

D1L73_cout_1 = D1_REG_Q[9] & !K1_RAMTMP0[1] & !D1L33 # !D1_REG_Q[9] & (!D1L33 # !K1_RAMTMP0[1]);
D1L73 = CARRY(D1L73_cout_1);


--E1L63 is generator_add:inst4|add~49 at LC_X18_Y4_N9
--operation mode is normal

E1L63 = J1_CLK & E1L9 # !J1_CLK & D1_REG_Q[9];


--E1L31 is generator_add:inst4|add~5 at LC_X19_Y4_N3
--operation mode is arithmetic

E1L31 = K1_RAMTMP2[2] $ D1_REG_Q[10] $ E1L11;

--E1L51 is generator_add:inst4|add~5COUT0 at LC_X19_Y4_N3
--operation mode is arithmetic

E1L51_cout_0 = K1_RAMTMP2[2] & !D1_REG_Q[10] & !E1L11 # !K1_RAMTMP2[2] & (!E1L11 # !D1_REG_Q[10]);
E1L51 = CARRY(E1L51_cout_0);

--E1L61 is generator_add:inst4|add~5COUT1 at LC_X19_Y4_N3
--operation mode is arithmetic

E1L61_cout_1 = K1_RAMTMP2[2] & !D1_REG_Q[10] & !E1L21 # !K1_RAMTMP2[2] & (!E1L21 # !D1_REG_Q[10]);
E1L61 = CARRY(E1L61_cout_1);


--D1_REG_Q[10] is generator_accB:inst3|REG_Q[10] at LC_X18_Y4_N2
--operation mode is arithmetic

D1_REG_Q[10]_carry_eqn = (!D1L92 & D1L63) # (D1L92 & D1L73);
D1_REG_Q[10]_lut_out = D1_REG_Q[10] $ K1_RAMTMP0[2] $ !D1_REG_Q[10]_carry_eqn;
D1_REG_Q[10] = DFFEA(D1_REG_Q[10]_lut_out, GLOBAL(J1_CLK), !GLOBAL(K1_TMP), , , , );

--D1L04 is generator_accB:inst3|REG_Q[10]~COUT0 at LC_X18_Y4_N2
--operation mode is arithmetic

D1L04_cout_0 = D1_REG_Q[10] & (K1_RAMTMP0[2] # !D1L63) # !D1_REG_Q[10] & K1_RAMTMP0[2] & !D1L63;
D1L04 = CARRY(D1L04_cout_0);

--D1L14 is generator_accB:inst3|REG_Q[10]~COUT1 at LC_X18_Y4_N2
--operation mode is arithmetic

D1L14_cout_1 = D1_REG_Q[10] & (K1_RAMTMP0[2] # !D1L73) # !D1_REG_Q[10] & K1_RAMTMP0[2] & !D1L73;
D1L14 = CARRY(D1L14_cout_1);


--E1L73 is generator_add:inst4|add~50 at LC_X18_Y4_N8
--operation mode is normal

E1L73 = J1_CLK & E1L31 # !J1_CLK & D1_REG_Q[10];


--E1L71 is generator_add:inst4|add~6 at LC_X19_Y4_N4
--operation mode is arithmetic

E1L71 = D1_REG_Q[11] $ K1_RAMTMP2[3] $ !E1L51;

--E1L81 is generator_add:inst4|add~6COUT at LC_X19_Y4_N4
--operation mode is arithmetic

E1L81 = E1L91;


--D1_REG_Q[11] is generator_accB:inst3|REG_Q[11] at LC_X18_Y4_N3
--operation mode is arithmetic

D1_REG_Q[11]_carry_eqn = (!D1L92 & D1L04) # (D1L92 & D1L14);
D1_REG_Q[11]_lut_out = K1_RAMTMP0[3] $ D1_REG_Q[11] $ D1_REG_Q[11]_carry_eqn;
D1_REG_Q[11] = DFFEA(D1_REG_Q[11]_lut_out, GLOBAL(J1_CLK), !GLOBAL(K1_TMP), , , , );

--D1L44 is generator_accB:inst3|REG_Q[11]~COUT0 at LC_X18_Y4_N3
--operation mode is arithmetic

D1L44_cout_0 = K1_RAMTMP0[3] & !D1_REG_Q[11] & !D1L04 # !K1_RAMTMP0[3] & (!D1L04 # !D1_REG_Q[11]);
D1L44 = CARRY(D1L44_cout_0);

--D1L54 is generator_accB:inst3|REG_Q[11]~COUT1 at LC_X18_Y4_N3
--operation mode is arithmetic

D1L54_cout_1 = K1_RAMTMP0[3] & !D1_REG_Q[11] & !D1L14 # !K1_RAMTMP0[3] & (!D1L14 # !D1_REG_Q[11]);
D1L54 = CARRY(D1L54_cout_1);


--E1L83 is generator_add:inst4|add~51 at LC_X15_Y4_N2
--operation mode is normal

E1L83 = J1_CLK & E1L71 # !J1_CLK & D1_REG_Q[11];


--E1L12 is generator_add:inst4|add~7 at LC_X19_Y4_N5
--operation mode is arithmetic

E1L12_carry_eqn = (!E1L81 & GND) # (E1L81 & VCC);
E1L12 = K1_RAMTMP2[4] $ D1_REG_Q[12] $ E1L12_carry_eqn;

--E1L32 is generator_add:inst4|add~7COUT0 at LC_X19_Y4_N5
--operation mode is arithmetic

E1L32_cout_0 = K1_RAMTMP2[4] & !D1_REG_Q[12] & !E1L81 # !K1_RAMTMP2[4] & (!E1L81 # !D1_REG_Q[12]);
E1L32 = CARRY(E1L32_cout_0);

--E1L42 is generator_add:inst4|add~7COUT1 at LC_X19_Y4_N5
--operation mode is arithmetic

E1L42_cout_1 = K1_RAMTMP2[4] & !D1_REG_Q[12] & !E1L81 # !K1_RAMTMP2[4] & (!E1L81 # !D1_REG_Q[12]);
E1L42 = CARRY(E1L42_cout_1);


--D1_REG_Q[12] is generator_accB:inst3|REG_Q[12] at LC_X18_Y4_N4
--operation mode is arithmetic

D1_REG_Q[12]_carry_eqn = (!D1L92 & D1L44) # (D1L92 & D1L54);
D1_REG_Q[12]_lut_out = K1_RAMTMP0[4] $ D1_REG_Q[12] $ !D1_REG_Q[12]_carry_eqn;
D1_REG_Q[12] = DFFEA(D1_REG_Q[12]_lut_out, GLOBAL(J1_CLK), !GLOBAL(K1_TMP), , , , );

--D1L74 is generator_accB:inst3|REG_Q[12]~COUT at LC_X18_Y4_N4
--operation mode is arithmetic

D1L74 = CARRY(K1_RAMTMP0[4] & (D1_REG_Q[12] # !D1L54) # !K1_RAMTMP0[4] & D1_REG_Q[12] & !D1L54);


--E1L93 is generator_add:inst4|add~52 at LC_X15_Y4_N6
--operation mode is normal

E1L93 = J1_CLK & E1L12 # !J1_CLK & D1_REG_Q[12];


--E1L52 is generator_add:inst4|add~8 at LC_X19_Y4_N6
--operation mode is arithmetic

E1L52_carry_eqn = (!E1L81 & E1L32) # (E1L81 & E1L42);
E1L52 = K1_RAMTMP2[5] $ D1_REG_Q[13] $ !E1L52_carry_eqn;

--E1L72 is generator_add:inst4|add~8COUT0 at LC_X19_Y4_N6
--operation mode is arithmetic

E1L72_cout_0 = K1_RAMTMP2[5] & (D1_REG_Q[13] # !E1L32) # !K1_RAMTMP2[5] & D1_REG_Q[13] & !E1L32;
E1L72 = CARRY(E1L72_cout_0);

--E1L82 is generator_add:inst4|add~8COUT1 at LC_X19_Y4_N6
--operation mode is arithmetic

E1L82_cout_1 = K1_RAMTMP2[5] & (D1_REG_Q[13] # !E1L42) # !K1_RAMTMP2[5] & D1_REG_Q[13] & !E1L42;
E1L82 = CARRY(E1L82_cout_1);


--D1_REG_Q[13] is generator_accB:inst3|REG_Q[13] at LC_X18_Y4_N5
--operation mode is arithmetic

D1_REG_Q[13]_carry_eqn = D1L74;
D1_REG_Q[13]_lut_out = K1_RAMTMP0[5] $ D1_REG_Q[13] $ D1_REG_Q[13]_carry_eqn;
D1_REG_Q[13] = DFFEA(D1_REG_Q[13]_lut_out, GLOBAL(J1_CLK), !GLOBAL(K1_TMP), , , , );

--D1L05 is generator_accB:inst3|REG_Q[13]~COUT0 at LC_X18_Y4_N5
--operation mode is arithmetic

D1L05_cout_0 = K1_RAMTMP0[5] & !D1_REG_Q[13] & !D1L74 # !K1_RAMTMP0[5] & (!D1L74 # !D1_REG_Q[13]);