test_double3.qsf

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# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		test_double3_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:09:38  AUGUST 20, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION 4.1
set_global_assignment -name VHDL_FILE generator_accb.vhd
set_global_assignment -name VHDL_FILE generator_add.vhd
set_global_assignment -name VHDL_FILE mux2s.vhd
set_global_assignment -name VHDL_FILE generator_reg81.vhd
set_global_assignment -name VHDL_FILE generator_reg82.vhd
set_global_assignment -name BDF_FILE test_double3.bdf

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_36 -to DA1CS
set_location_assignment PIN_37 -to WRN
set_location_assignment PIN_55 -to DA2CS
set_location_assignment PIN_54 -to XFER
set_location_assignment PIN_16 -to CLK
set_location_assignment PIN_94 -to CS
set_location_assignment PIN_35 -to DY
set_location_assignment PIN_77 -to WR
set_location_assignment PIN_76 -to RD
set_location_assignment PIN_78 -to ALE
set_location_assignment PIN_31 -to ADCS
set_location_assignment PIN_75 -to P0\[0\]
set_location_assignment PIN_74 -to P0\[1\]
set_location_assignment PIN_73 -to P0\[2\]
set_location_assignment PIN_72 -to P0\[3\]
set_location_assignment PIN_71 -to P0\[4\]
set_location_assignment PIN_70 -to P0\[5\]
set_location_assignment PIN_69 -to P0\[6\]
set_location_assignment PIN_68 -to P0\[7\]
set_location_assignment PIN_85 -to P2\[0\]
set_location_assignment PIN_84 -to P2\[1\]
set_location_assignment PIN_83 -to P2\[2\]
set_location_assignment PIN_82 -to P2\[3\]
set_location_assignment PIN_79 -to P2\[4\]
set_location_assignment PIN_49 -to Q1\[0\]
set_location_assignment PIN_48 -to Q1\[1\]
set_location_assignment PIN_47 -to Q1\[2\]
set_location_assignment PIN_42 -to Q1\[3\]
set_location_assignment PIN_41 -to Q1\[4\]
set_location_assignment PIN_40 -to Q1\[5\]
set_location_assignment PIN_39 -to Q1\[6\]
set_location_assignment PIN_38 -to Q1\[7\]
set_location_assignment PIN_67 -to Q2\[0\]
set_location_assignment PIN_62 -to Q2\[1\]
set_location_assignment PIN_61 -to Q2\[2\]
set_location_assignment PIN_60 -to Q2\[3\]
set_location_assignment PIN_59 -to Q2\[4\]
set_location_assignment PIN_58 -to Q2\[5\]
set_location_assignment PIN_57 -to Q2\[6\]
set_location_assignment PIN_56 -to Q2\[7\]

# Timing Assignments
# ==================
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS OFF

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name TOP_LEVEL_ENTITY test_double3

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C3T144C8
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name MAX7000B_VCCIO_IOBANK1 3.3V
set_global_assignment -name MAX7000B_VCCIO_IOBANK2 3.3V

# Timing Analysis Assignments
# ===========================
set_global_assignment -name EXCLUDE_TPD_PATHS_LESS_THAN 0.0NS

# Simulator Assignments
# =====================
set_global_assignment -name START_TIME 0.0ns
set_global_assignment -name GLITCH_INTERVAL 0.0ns
set_global_assignment -name END_TIME 10.0us

# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT off