📄 test_double3.map.rpt
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|-- cntr_0b7:auto_generated
|-- BUS_51:inst9
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------------------------------------+
; |test_double3 ; 111 (0) ; 80 ; 4096 ; 38 ; 0 ; 31 (0) ; 25 (0) ; 55 (0) ; 29 (0) ; |test_double3 ;
; |BUS_51:inst9| ; 55 (55) ; 43 ; 0 ; 0 ; 0 ; 12 (12) ; 8 (8) ; 35 (35) ; 0 (0) ; |test_double3|BUS_51:inst9 ;
; |FREDEVIDER8:inst8| ; 6 (2) ; 5 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 4 (0) ; 4 (0) ; |test_double3|FREDEVIDER8:inst8 ;
; |lpm_counter:COUNTER_rtl_0| ; 4 (0) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (0) ; 4 (0) ; |test_double3|FREDEVIDER8:inst8|lpm_counter:COUNTER_rtl_0 ;
; |cntr_0b7:auto_generated| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 4 (4) ; |test_double3|FREDEVIDER8:inst8|lpm_counter:COUNTER_rtl_0|cntr_0b7:auto_generated ;
; |generator_accB:inst3| ; 16 (16) ; 16 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 16 (16) ; 16 (16) ; |test_double3|generator_accB:inst3 ;
; |generator_add:inst4| ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 18 (18) ; 0 (0) ; 0 (0) ; 9 (9) ; |test_double3|generator_add:inst4 ;
; |generator_reg81:inst6| ; 8 (8) ; 8 ; 0 ; 0 ; 0 ; 0 (0) ; 8 (8) ; 0 (0) ; 0 (0) ; |test_double3|generator_reg81:inst6 ;
; |generator_reg82:inst7| ; 8 (8) ; 8 ; 0 ; 0 ; 0 ; 0 (0) ; 8 (8) ; 0 (0) ; 0 (0) ; |test_double3|generator_reg82:inst7 ;
; |lpm_rom0:inst| ; 0 (0) ; 0 ; 4096 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |test_double3|lpm_rom0:inst ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 4096 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |test_double3|lpm_rom0:inst|altsyncram:altsyncram_component ;
; |altsyncram_ccr:auto_generated| ; 0 (0) ; 0 ; 4096 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |test_double3|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated ;
+------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------------------------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in G:/ywh/QUARTUSII/sinWAVEgenerator/test_double3.map.eqn.
+-------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+-------------------------------------------------------------------+-----------------+
; File Name ; Used in Netlist ;
+-------------------------------------------------------------------+-----------------+
; generator_accb.vhd ; yes ;
; generator_add.vhd ; yes ;
; mux2s.vhd ; yes ;
; generator_reg81.vhd ; yes ;
; generator_reg82.vhd ; yes ;
; test_double3.bdf ; yes ;
; G:/ywh/QUARTUSII/sinWAVEgenerator/BUSTRI.vhd ; yes ;
; d:/altera/quartus41/libraries/megafunctions/lpm_bustri.tdf ; yes ;
; G:/ywh/QUARTUSII/sinWAVEgenerator/BUS_51.vhd ; yes ;
; G:/ywh/QUARTUSII/sinWAVEgenerator/FREDEVIDER8.vhd ; yes ;
; G:/ywh/QUARTUSII/sinWAVEgenerator/lpm_rom0.vhd ; yes ;
; d:/altera/quartus41/libraries/megafunctions/altsyncram.tdf ; yes ;
; d:/altera/quartus41/libraries/megafunctions/stratix_ram_block.inc ; yes ;
; G:/ywh/QUARTUSII/sinWAVEgenerator/db/altsyncram_ccr.tdf ; yes ;
; d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf ; yes ;
; d:/altera/quartus41/libraries/megafunctions/lpm_constant.inc ; yes ;
; G:/ywh/QUARTUSII/sinWAVEgenerator/db/cntr_0b7.tdf ; yes ;
+-------------------------------------------------------------------+-----------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource ; Usage ;
+-----------------------------------+---------+
; Logic cells ; 111 ;
; Total combinational functions ; 86 ;
; Total 4-input functions ; 36 ;
; Total 3-input functions ; 18 ;
; Total 2-input functions ; 28 ;
; Total 1-input functions ; 4 ;
; Total 0-input functions ; 0 ;
; Combinational cells for routing ; 0 ;
; Total registers ; 80 ;
; Total logic cells in carry chains ; 29 ;
; I/O pins ; 38 ;
; Total memory bits ; 4096 ;
; Maximum fan-out node ; CLK ;
; Maximum fan-out ; 48 ;
; Total fan-out ; 588 ;
; Average fan-out ; 3.75 ;
+-----------------------------------+---------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+----------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+------------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+----------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+------------+
; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 512 ; 8 ; -- ; -- ; 4096 ; Sin512.mif ;
+----------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
Info: Processing started: Sat Aug 20 15:12:52 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off test_double3 -c test_double3
Info: Found 2 design units, including 1 entities, in source file generator_accb.vhd
Info: Found design unit 1: generator_accB-acc_arch
Info: Found entity 1: generator_accB
Info: Found 2 design units, including 1 entities, in source file generator_add.vhd
Info: Found design unit 1: generator_add-add_anGen_arch
Info: Found entity 1: generator_add
Info: Found 2 design units, including 1 entities, in source file mux2s.vhd
Info: Found design unit 1: MUX2S-ART
Info: Found entity 1: MUX2S
Info: Found 2 design units, including 1 entities, in source file generator_reg81.vhd
Info: Found design unit 1: generator_reg81-reg_arch8
Info: Found entity 1: generator_reg81
Info: Found 2 design units, including 1 entities, in source file generator_reg82.vhd
Info: Found design unit 1: generator_reg82-reg_arch8
Info: Found entity 1: generator_reg82
Info: Found 1 design units, including 1 entities, in source file test_double3.bdf
Info: Found entity 1: test_double3
Info: Using design file BUSTRI.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: BUSTRI-SYN
Info: Found entity 1: BUSTRI
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/lpm_bustri.tdf
Info: Found entity 1: lpm_bustri
Info: Using design file BUS_51.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: BUS_51-ART
Info: Found entity 1: BUS_51
Info: Using design file FREDEVIDER8.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: FREDEVIDER8-ART
Info: Found entity 1: FREDEVIDER8
Info: Using design file lpm_rom0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: lpm_rom0-SYN
Info: Found entity 1: lpm_rom0
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/altsyncram.tdf
Info: Found entity 1: altsyncram
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ccr.tdf
Info: Found entity 1: altsyncram_ccr
Warning: VHDL Process Statement warning at generator_accb.vhd(35): signal a is in statement, but is not in sensitivity list
Info: Ignored 9 buffer(s)
Info: Ignored 9 SOFT buffer(s)
Info: Inferred 1 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: FREDEVIDER8:inst8|COUNTER[0]~8
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file db/cntr_0b7.tdf
Info: Found entity 1: cntr_0b7
Warning: Converted TRI buffer to OR gate or removed OPNDRN
Warning: Converting TRI node BUSTRI:inst1|lpm_bustri:lpm_bustri_component|din[6] that feeds logic to an OR gate
Warning: Converting TRI node BUSTRI:inst1|lpm_bustri:lpm_bustri_component|din[5] that feeds logic to an OR gate
Warning: Converting TRI node BUSTRI:inst1|lpm_bustri:lpm_bustri_component|din[4] that feeds logic to an OR gate
Warning: Converting TRI node BUSTRI:inst1|lpm_bustri:lpm_bustri_component|din[3] that feeds logic to an OR gate
Warning: Converting TRI node BUSTRI:inst1|lpm_bustri:lpm_bustri_component|din[2] that feeds logic to an OR gate
Warning: Converting TRI node BUSTRI:inst1|lpm_bustri:lpm_bustri_component|din[1] that feeds logic to an OR gate
Warning: Converting TRI node BUSTRI:inst1|lpm_bustri:lpm_bustri_component|din[0] that feeds logic to an OR gate
Warning: Converting TRI node BUSTRI:inst1|lpm_bustri:lpm_bustri_component|din[7] that feeds logic to an OR gate
Warning: Output pins are stuck at VCC or GND
Warning: Pin XFER stuck at GND
Warning: Pin DA1CS stuck at GND
Warning: Pin DA2CS stuck at GND
Warning: Pin WRN stuck at GND
Warning: Design contains 5 input pin(s) that do not drive logic
Warning: No output dependent on input pin P2[4]
Warning: No output dependent on input pin P2[3]
Warning: No output dependent on input pin P2[2]
Warning: No output dependent on input pin P2[1]
Warning: No output dependent on input pin P2[0]
Info: Implemented 157 device resources after synthesis - the final resource count might be different
Info: Implemented 10 input pins
Info: Implemented 20 output pins
Info: Implemented 8 bidirectional pins
Info: Implemented 111 logic cells
Info: Implemented 8 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 21 warnings
Info: Processing ended: Sat Aug 20 15:12:56 2005
Info: Elapsed time: 00:00:04
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