test_double3.tan.summary

DDS锯齿波发生器： 开发平台：maxplus＋FPGA 功能： 输出X路扫屏锯齿波。频率可用键盘精确控制

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 7.955 ns
From           : WR
To             : BUS_51:inst9|RAMTMP3[7]
From Clock     : 
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 11.464 ns
From           : generator_reg81:inst6|TEMP_Q_1[7]
To             : Q1[7]
From Clock     : CLK
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.179 ns
From           : P0[0]
To             : BUS_51:inst9|LATCH_ADDRES[0]
From Clock     : 
To Clock       : ALE
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 6.457 ns
From           : BUS_51:inst9|P0_OUT[7]
To             : P0[7]
From Clock     : CLK
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 92.03 MHz ( period = 10.866 ns )
From           : BUS_51:inst9|RAMTMP3[7]
To             : lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg7
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Hold: 'CLK'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : BUS_51:inst9|RAMTMP0[7]
To             : generator_accB:inst3|REG_Q[15]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 152

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 152

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