test_double3.pin

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 -- Copyright (C) 1991-2004 Altera Corporation
 -- Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 -- support information,  device programming or simulation file,  and any other
 -- associated  documentation or information  provided by  Altera  or a partner
 -- under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 -- to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 -- other  use  of such  megafunction  design,  netlist,  support  information,
 -- device programming or simulation file,  or any other  related documentation
 -- or information  is prohibited  for  any  other purpose,  including, but not
 -- limited to  modification,  reverse engineering,  de-compiling, or use  with
 -- any other  silicon devices,  unless such use is  explicitly  licensed under
 -- a separate agreement with  Altera  or a megafunction partner.  Title to the
 -- intellectual property,  including patents,  copyrights,  trademarks,  trade
 -- secrets,  or maskworks,  embodied in any such megafunction design, netlist,
 -- support  information,  device programming or simulation file,  or any other
 -- related documentation or information provided by  Altera  or a megafunction
 -- partner, remains with Altera, the megafunction partner, or their respective
 -- licensors. No other licenses, including any licenses needed under any third
 -- party's intellectual property, are provided herein.
 -- 
 -- This is a Quartus II output file. It is for reporting purposes only, and is
 -- not intended for use as a Quartus II input file. This file cannot be used
 -- to make Quartus II pin assignments - for instructions on how to make pin
 -- assignments, please see Quartus II help.
 ---------------------------------------------------------------------------------



 ---------------------------------------------------------------------------------
 -- NC            : No Connect. This pin has no internal connection to the device.
 -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.5V).
 -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
 --                 of its bank.
 --					Bank 1:		3.3V
 --					Bank 2:		3.3V
 --					Bank 3:		3.3V
 --					Bank 4:		3.3V
 -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
 --					It can also be used to report unused dedicated pins. The connection
 --					on the board for unused dedicated pins depends on whether this will
 --					be used in a future design. One example is device migration. When
 --					using device migration, refer to the device pin-tables. If it is a
 --					GND pin in the pin table or if it will not be used in a future design
 --					for another purpose the it MUST be connected to GND. If it is an unused
 --					dedicated pin, then it can be connected to a valid signal on the board
 --					(low, high, or toggling) if that signal is required for a different
 --					revision of the design.
 -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
 --					This pin should be connected to GND. It may also be connected  to a
 --					valid signal  on the board  (low, high, or toggling)  if that signal
 --					is required for a different revision of the design.
 -- GND*          : Unused  I/O  pin.   This pin can either be left unconnected or
 --           	    connected to GND.  Connecting this pin to GND will improve the
 --           	    device's immunity to noise.
 ---------------------------------------------------------------------------------

Quartus II Version 4.1 Build 181 06/29/2004 SJ Full Version
CHIP  "test_double3"  ASSIGNED TO AN: EP1C3T144C8

Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
-------------------------------------------------------------------------------------------------------------
GND*                         : 1         :        :                   :         : 1         :                
GND*                         : 2         :        :                   :         : 1         :                
GND*                         : 3         :        :                   :         : 1         :                
GND*                         : 4         :        :                   :         : 1         :                
GND*                         : 5         :        :                   :         : 1         :                
GND*                         : 6         :        :                   :         : 1         :                
GND*                         : 7         :        :                   :         : 1         :                
VCCIO1                       : 8         : power  :                   : 3.3V    : 1         :                
GND                          : 9         : gnd    :                   :         : 1         :                
GND*                         : 10        :        :                   :         : 1         :                
GND*                         : 11        :        :                   :         : 1         :                
~nCSO~ / GND*                : 12        : output : LVTTL             :         : 1         : N              
DATA0                        : 13        : input  :                   :         : 1         :                
nCONFIG                      : 14        :        :                   :         : 1         :                
VCCA_PLL1                    : 15        : power  :                   : 1.5V    : 1         :                
CLK                          : 16        : input  : LVTTL             :         : 1         : Y              
GND+                         : 17        :        :                   :         : 1         :                
GNDA_PLL1                    : 18        : gnd    :                   :         : 1         :                
GNDG_PLL1                    : 19        : gnd    :                   :         : 1         :                
nCEO                         : 20        :        :                   :         : 1         :                
nCE                          : 21        :        :                   :         : 1         :                
MSEL0                        : 22        :        :                   :         : 1         :                
MSEL1                        : 23        :        :                   :         : 1         :                
DCLK                         : 24        : bidir  :                   :         : 1         :                
~ASDO~ / GND*                : 25        : output : LVTTL             :         : 1         : N              
GND*                         : 26        :        :                   :         : 1         :                
GND*                         : 27        :        :                   :         : 1         :                
GND*                         : 28        :        :                   :         : 1         :                
VCCIO1                       : 29        : power  :                   : 3.3V    : 1         :                
GND                          : 30        : gnd    :                   :         : 1         :                
GND*                         : 31        :        :                   :         : 1         :                
GND*                         : 32        :        :                   :         : 1         :                
GND*                         : 33        :        :                   :         : 1         :                
GND*                         : 34        :        :                   :         : 1         :                
GND*                         : 35        :        :                   :         : 1         :                
DA1CS                        : 36        : output : LVTTL             :         : 1         : Y              
WRN                          : 37        : output : LVTTL             :         : 4         : Y              
Q1[7]                        : 38        : output : LVTTL             :         : 4         : Y              
Q1[6]                        : 39        : output : LVTTL             :         : 4         : Y              
Q1[5]                        : 40        : output : LVTTL             :         : 4         : Y              
Q1[4]                        : 41        : output : LVTTL             :         : 4         : Y              
Q1[3]                        : 42        : output : LVTTL             :         : 4         : Y