fir_filter_da_machine.v

用verilog 代码编写的179阶FIR数字滤波器

//FIR 数字滤波器 用DA算法实现，封装了：控制模块，数据预处理模块，滤波模块
//滤波器处理速率为：时钟频率/13

module FIR_filter_DA_machine(y_out,clk,reset,x_in);
//端口说明
output [29:0] y_out;                                            //信号线连接滤波器输出 
input  clk,reset;
input  [11:0] x_in;                                         //数据预处理器输入数据端

//内部信号线
wire filter_ctrl,load_sum_ctrl,reset_ctrl,ready;            //控制信号连线                         
                                                                                                   
                                                          
                                                                                                   
wire [12:0]  m0, m1,m2,m3,m4,m5,m6,m7,m8,m9,m10,            //数据预处理器输出连线                 
                m11, m12, m13, m14, m15, m16, m17, m18, m19, m20,                                  
                m21, m22, m23, m24, m25,  m26,m27, m28, m29, m30,                                  
                m31, m32, m33, m34;                                                                
                                                                                                   
                                                   
                                                            
                                                                                                   
//控制模块                                                                                           
control_m            control_machine(filter_ctrl,load_sum_ctrl,reset_ctrl,clk,reset,ready);          
                                                                                                   
//数据预处理模块                                                                                     
data_pre_process_m   data_pre_process_m(m0,m1,m2,m3,m4,m5,m6,m7,m8,m9,m10,                         
                                        m11, m12, m13, m14, m15, m16, m17, m18, m19, m20,          
                                        m21, m22, m23, m24, m25,  m26,m27, m28, m29, m30,          
                                        m31, m32, m33, m34,x_in,reset_ctrl,load_sum_ctrl);         
//滤波模块                                                                                           
da_alg_filter_m      da_filter_m(y_out,ready,m0,m1,m2,m3,m4,m5,m6,m7,m8,m9,m10,                    
                                             m11, m12, m13, m14, m15, m16, m17, m18, m19, m20,     
                                             m21, m22, m23, m24, m25,  m26,m27, m28, m29, m30,     
                                             m31,m32,m33,m34,clk,filter_ctrl,reset_ctrl);   
                                             
endmodule