flash.v

来自「maxII16_cpu,altera的maxII系列的16位cpu」· Verilog 代码 · 共 71 行

module flash(
	clock,
	address,
	data_out,
	go_read,
	chipselect,
	complete,
	osc);

input			clock;
input	[8:0]	address;
input			go_read;
input			chipselect;

output			osc;
output			complete;
output	[15:0]	data_out;
	
parameter idle = 0;
parameter s1 = 1;
parameter s2 = 2;
parameter s3 = 3;

reg				complete;
reg				flash_nread;
reg		[1:0]	flash_nbusy;
reg		[1:0]	flash_data_valid;
reg		[15:0]	do [1:0];
reg		[4:0]	fsm, next_state;

UFM				flash(.addr(address), .data_valid(flash_data_valid[0]), .do(do[0]), .nbusy(flash_nbusy[0]),
					.nread(flash_nread), .osc(osc));

assign data_out = do[1];

always @ (posedge clock) begin
	fsm <= next_state;
	flash_data_valid[1] <= flash_data_valid[0];
	flash_nbusy[1] <= flash_nbusy[0];
	flash_nread <= ~(go_read & chipselect);
	do[1] <= do[0];
end

always @ (fsm, chipselect, go_read, flash_nread, flash_data_valid, flash_nbusy) begin
	complete <= 1'b0;
	next_state <= fsm;
	case(fsm)
		idle:begin
			if((flash_nbusy[1] & go_read & chipselect) == 1'b1) begin
				next_state <= s1;
			end
		end
		
		s1:begin
			if(flash_data_valid[1] == 1'b1) begin
				next_state <= s2;
			end
		end
		
		s2:begin
			next_state <= s3;
		end
		
		s3:begin
			complete <= 1'b1;
			next_state <= idle;
		end
	endcase
end

endmodule