smallram.v

来自「maxII16_cpu,altera的maxII系列的16位cpu」· Verilog 代码 · 共 85 行

module smallram(
	clock,
	address,
	data_in,
	data_out,
	go_read,
	go_write,
	chipselect,
	complete);

input			clock;
input			go_read;
input			go_write;
input			chipselect;
input	[2:0]	address;
input	[15:0]	data_in;

output	[15:0]	data_out;
output			complete;

reg		[15:0]	data_out;
reg		[7:0]	data_ena;
reg		[15:0]	data[7:0];

assign	complete = (go_read | go_write) & chipselect;

always @ (posedge clock) begin
	if(data_ena[0])
		data[0] <= data_in;
	if(data_ena[1])
		data[1] <= data_in;
	if(data_ena[2])
		data[2] <= data_in;
	if(data_ena[3])
		data[3] <= data_in;
	if(data_ena[4])
		data[4] <= data_in;
	if(data_ena[5])
		data[5] <= data_in;
	if(data_ena[6])
		data[6] <= data_in;
	if(data_ena[7])
		data[7] <= data_in;
end

always @ (address, data, go_write, chipselect) begin
	data_out <= 0;
	data_ena <= 0;
	case(address)
		0:begin
			data_out <= data[0];
			data_ena[0] <= go_write & chipselect;
		end
		1:begin
			data_out <= data[1];
			data_ena[1] <= go_write & chipselect;
		end
		2:begin
			data_out <= data[2];
			data_ena[2] <= go_write & chipselect;
		end
		3:begin
			data_out <= data[3];
			data_ena[3] <= go_write & chipselect;
		end
		4:begin
			data_out <= data[4];
			data_ena[4] <= go_write & chipselect;
		end
		5:begin
			data_out <= data[5];
			data_ena[5] <= go_write & chipselect;
		end
		6:begin
			data_out <= data[6];
			data_ena[6] <= go_write & chipselect;
		end
		7:begin
			data_out <= data[7];
			data_ena[7] <= go_write & chipselect;
		end
	endcase
end

endmodule