sram_controller.v

来自「maxII16_cpu,altera的maxII系列的16位cpu」· Verilog 代码 · 共 105 行

module sram_controller(
	clock,
	data_in,
	go_read,
	go_write,
	chipselect,
	complete,

	data,
	noe,
	nwe,
	ncs);

parameter	idle = 0;
parameter	s1 = 1;
parameter	s2 = 2;
parameter	s3 = 3;
parameter	s4 = 4;
parameter	s5 = 5;

input			clock;
input			go_read;
input			go_write;
input			chipselect;
input	[7:0]	data_in;

output			complete;
output			noe;
output			nwe;
output			ncs;

inout	[7:0]	data;

reg				complete;
reg		[5:0]	fsm, next_state;
reg				oe, oe_data;
reg				we, we_data;
reg				cs, cs_data;
reg				doe;
reg				d_ena;

assign data = (doe == 1'b1) ? data_in : 8'bz;
assign nwe = ~we;
assign noe = ~oe;
assign ncs = ~cs;

always @ (posedge clock) begin
	fsm <= next_state;
	oe <= oe_data;
	we <= we_data;
	cs <= cs_data;
	doe <= d_ena;
end

always @ (fsm, go_read, go_write, chipselect) begin
	d_ena <= 1'b0;
	we_data <= 1'b0;
	oe_data <= 1'b0;
	cs_data <= 1'b0;
	complete <= 1'b0;
	next_state <= fsm;
	case(fsm)
		idle:begin
			if((go_read & chipselect) == 1'b1) begin
				oe_data <= 1'b1;
				cs_data <= 1'b1;
				next_state <= s1;
			end
			if((go_write & chipselect) == 1'b1) begin
				d_ena <= 1'b1;
				cs_data <= 1'b1;
				next_state <= s2;
			end
		end
		
		s1:begin
			complete <= 1'b1;
			next_state <= idle;
		end
		
		s2:begin
			d_ena <= 1'b1;
			cs_data <= 1'b1;
			we_data <= 1'b1;
			next_state <= s3;
		end
		
		s3:begin
			d_ena <= 1'b1;
			cs_data <= 1'b1;
			next_state <= s4;
		end
		
		s4:begin
			next_state <= s5;
		end
		
		s5:begin
			complete <= 1'b1;
			next_state <= idle;
		end
	endcase
end

endmodule