shift.map.qmsg

本程序实现数字的前向或者后向移动功能

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 20 18:49:30 2006 " "Info: Processing started: Wed Dec 20 18:49:30 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off shift -c shift " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shift -c shift" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shift.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file shift.v" { { "Info" "ISGN_ENTITY_NAME" "1 shift " "Info: Found entity 1: shift" {  } { { "shift.v" "" { Text "F:/课程/SOC设计/作业/shifttest/zhengshi/shift.v" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "shift " "Info: Elaborating entity \"shift\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "out\[4\] GND " "Warning: Pin \"out\[4\]\" stuck at GND" {  } { { "shift.v" "" { Text "F:/课程/SOC设计/作业/shifttest/zhengshi/shift.v" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "out\[5\] GND " "Warning: Pin \"out\[5\]\" stuck at GND" {  } { { "shift.v" "" { Text "F:/课程/SOC设计/作业/shifttest/zhengshi/shift.v" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "out\[6\] GND " "Warning: Pin \"out\[6\]\" stuck at GND" {  } { { "shift.v" "" { Text "F:/课程/SOC设计/作业/shifttest/zhengshi/shift.v" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "out\[7\] GND " "Warning: Pin \"out\[7\]\" stuck at GND" {  } { { "shift.v" "" { Text "F:/课程/SOC设计/作业/shifttest/zhengshi/shift.v" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "4 " "Warning: Design contains 4 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in\[4\] " "Warning: No output dependent on input pin \"in\[4\]\"" {  } { { "shift.v" "" { Text "F:/课程/SOC设计/作业/shifttest/zhengshi/shift.v" 10 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in\[5\] " "Warning: No output dependent on input pin \"in\[5\]\"" {  } { { "shift.v" "" { Text "F:/课程/SOC设计/作业/shifttest/zhengshi/shift.v" 10 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in\[6\] " "Warning: No output dependent on input pin \"in\[6\]\"" {  } { { "shift.v" "" { Text "F:/课程/SOC设计/作业/shifttest/zhengshi/shift.v" 10 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in\[7\] " "Warning: No output dependent on input pin \"in\[7\]\"" {  } { { "shift.v" "" { Text "F:/课程/SOC设计/作业/shifttest/zhengshi/shift.v" 10 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "33 " "Info: Implemented 33 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "13 " "Info: Implemented 13 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 20 18:49:33 2006 " "Info: Processing ended: Wed Dec 20 18:49:33 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}