shift.map.rpt

本程序实现数字的前向或者后向移动功能

; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                        ;
+----------------------------------+-----------------+------------------------+-------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                    ;
+----------------------------------+-----------------+------------------------+-------------------------------------------------+
; shift.v                          ; yes             ; User Verilog HDL File  ; F:/课程/SOC设计/作业/shifttest/zhengshi/shift.v ;
+----------------------------------+-----------------+------------------------+-------------------------------------------------+


+---------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary             ;
+---------------------------------------------+-----------+
; Resource                                    ; Usage     ;
+---------------------------------------------+-----------+
; Total logic elements                        ; 8         ;
;     -- Combinational with no register       ; 8         ;
;     -- Register only                        ; 0         ;
;     -- Combinational with a register        ; 0         ;
;                                             ;           ;
; Logic element usage by number of LUT inputs ;           ;
;     -- 4 input functions                    ; 0         ;
;     -- 3 input functions                    ; 0         ;
;     -- 2 input functions                    ; 8         ;
;     -- 1 input functions                    ; 0         ;
;     -- 0 input functions                    ; 0         ;
;         -- Combinational cells for routing  ; 0         ;
;                                             ;           ;
; Logic elements by mode                      ;           ;
;     -- normal mode                          ; 8         ;
;     -- arithmetic mode                      ; 0         ;
;     -- qfbk mode                            ; 0         ;
;     -- register cascade mode                ; 0         ;
;     -- synchronous clear/load mode          ; 0         ;
;     -- asynchronous clear/load mode         ; 0         ;
;                                             ;           ;
; Total registers                             ; 0         ;
; I/O pins                                    ; 25        ;
; Maximum fan-out node                        ; direction ;
; Maximum fan-out                             ; 8         ;
; Total fan-out                               ; 24        ;
; Average fan-out                             ; 0.73      ;
+---------------------------------------------+-----------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                             ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |shift                     ; 8 (8)       ; 0            ; 0           ; 0     ; 0    ; 0      ; 0            ; 0       ; 0         ; 0         ; 25   ; 0            ; 8 (8)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |shift              ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |shift ;
+----------------+-------+----------------------------------------------+
; Parameter Name ; Value ; Type                                         ;
+----------------+-------+----------------------------------------------+
; width          ; 12    ; Integer                                      ;
; shift_digi     ; 8     ; Integer                                      ;
+----------------+-------+----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Dec 20 18:49:30 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shift -c shift
Info: Found 1 design units, including 1 entities, in source file shift.v
    Info: Found entity 1: shift
Info: Elaborating entity "shift" for the top level hierarchy
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "out[4]" stuck at GND
    Warning: Pin "out[5]" stuck at GND
    Warning: Pin "out[6]" stuck at GND
    Warning: Pin "out[7]" stuck at GND
Warning: Design contains 4 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "in[4]"
    Warning: No output dependent on input pin "in[5]"
    Warning: No output dependent on input pin "in[6]"
    Warning: No output dependent on input pin "in[7]"
Info: Implemented 33 device resources after synthesis - the final resource count might be different
    Info: Implemented 13 input pins
    Info: Implemented 12 output pins
    Info: Implemented 8 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
    Info: Processing ended: Wed Dec 20 18:49:33 2006
    Info: Elapsed time: 00:00:04