more1.map.rpt

本程序对输入的任意多个二进制数字进行判别（0和1的个数）

; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                    ;
+----------------------------------+-----------------+------------------------+---------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                ;
+----------------------------------+-----------------+------------------------+---------------------------------------------+
; more1.v                          ; yes             ; User Verilog HDL File  ; F:/课程/SOC设计/作业/homework/more1/more1.v ;
+----------------------------------+-----------------+------------------------+---------------------------------------------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+---------------------------------------------+---------+
; Resource                                    ; Usage   ;
+---------------------------------------------+---------+
; Total logic elements                        ; 26      ;
;     -- Combinational with no register       ; 26      ;
;     -- Register only                        ; 0       ;
;     -- Combinational with a register        ; 0       ;
;                                             ;         ;
; Logic element usage by number of LUT inputs ;         ;
;     -- 4 input functions                    ; 3       ;
;     -- 3 input functions                    ; 7       ;
;     -- 2 input functions                    ; 14      ;
;     -- 1 input functions                    ; 2       ;
;     -- 0 input functions                    ; 0       ;
;         -- Combinational cells for routing  ; 0       ;
;                                             ;         ;
; Logic elements by mode                      ;         ;
;     -- normal mode                          ; 16      ;
;     -- arithmetic mode                      ; 10      ;
;     -- qfbk mode                            ; 0       ;
;     -- register cascade mode                ; 0       ;
;     -- synchronous clear/load mode          ; 0       ;
;     -- asynchronous clear/load mode         ; 0       ;
;                                             ;         ;
; Total registers                             ; 0       ;
; Total logic cells in carry chains           ; 13      ;
; I/O pins                                    ; 14      ;
; Maximum fan-out node                        ; Add1~83 ;
; Maximum fan-out                             ; 3       ;
; Total fan-out                               ; 64      ;
; Average fan-out                             ; 1.60    ;
+---------------------------------------------+---------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                             ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |more1                     ; 26 (26)     ; 0            ; 0           ; 0     ; 0    ; 0      ; 0            ; 0       ; 0         ; 0         ; 14   ; 0            ; 26 (26)      ; 0 (0)             ; 0 (0)            ; 13 (13)         ; 0 (0)      ; |more1              ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sat Dec 30 13:00:00 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off more1 -c more1
Info: Found 1 design units, including 1 entities, in source file more1.v
    Info: Found entity 1: more1
Info: Elaborating entity "more1" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at more1.v(17): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at more1.v(21): truncated value with size 32 to match size of target (1)
Warning (10240): Verilog HDL Always Construct warning at more1.v(12): inferring latch(es) for variable "count", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at more1.v(10): inferred latch for "count[4]"
Info (10041): Verilog HDL or VHDL info at more1.v(10): inferred latch for "count[3]"
Info (10041): Verilog HDL or VHDL info at more1.v(10): inferred latch for "count[2]"
Info (10041): Verilog HDL or VHDL info at more1.v(10): inferred latch for "count[1]"
Warning (10240): Verilog HDL Always Construct warning at more1.v(12): inferring latch(es) for variable "i", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at more1.v(10): inferred latch for "i[4]"
Info (10041): Verilog HDL or VHDL info at more1.v(10): inferred latch for "i[3]"
Info (10041): Verilog HDL or VHDL info at more1.v(10): inferred latch for "i[2]"
Info (10041): Verilog HDL or VHDL info at more1.v(10): inferred latch for "i[1]"
Info: Implemented 40 device resources after synthesis - the final resource count might be different
    Info: Implemented 13 input pins
    Info: Implemented 1 output pins
    Info: Implemented 26 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Processing ended: Sat Dec 30 13:00:01 2006
    Info: Elapsed time: 00:00:01