more1.map.qmsg

本程序对输入的任意多个二进制数字进行判别（0和1的个数）

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 30 13:00:00 2006 " "Info: Processing started: Sat Dec 30 13:00:00 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off more1 -c more1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off more1 -c more1" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "more1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file more1.v" { { "Info" "ISGN_ENTITY_NAME" "1 more1 " "Info: Found entity 1: more1" {  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "more1 " "Info: Elaborating entity \"more1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 more1.v(17) " "Warning (10230): Verilog HDL assignment warning at more1.v(17): truncated value with size 32 to match size of target (4)" {  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 17 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 more1.v(21) " "Warning (10230): Verilog HDL assignment warning at more1.v(21): truncated value with size 32 to match size of target (1)" {  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 21 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "count more1.v(12) " "Warning (10240): Verilog HDL Always Construct warning at more1.v(12): inferring latch(es) for variable \"count\", which holds its previous value in one or more paths through the always construct" {  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 12 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "count\[4\] more1.v(10) " "Info (10041): Verilog HDL or VHDL info at more1.v(10): inferred latch for \"count\[4\]\"" {  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 10 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "count\[3\] more1.v(10) " "Info (10041): Verilog HDL or VHDL info at more1.v(10): inferred latch for \"count\[3\]\"" {  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 10 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "count\[2\] more1.v(10) " "Info (10041): Verilog HDL or VHDL info at more1.v(10): inferred latch for \"count\[2\]\"" {  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 10 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "count\[1\] more1.v(10) " "Info (10041): Verilog HDL or VHDL info at more1.v(10): inferred latch for \"count\[1\]\"" {  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 10 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "i more1.v(12) " "Warning (10240): Verilog HDL Always Construct warning at more1.v(12): inferring latch(es) for variable \"i\", which holds its previous value in one or more paths through the always construct" {  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 12 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "i\[4\] more1.v(10) " "Info (10041): Verilog HDL or VHDL info at more1.v(10): inferred latch for \"i\[4\]\"" {  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 10 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "i\[3\] more1.v(10) " "Info (10041): Verilog HDL or VHDL info at more1.v(10): inferred latch for \"i\[3\]\"" {  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 10 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "i\[2\] more1.v(10) " "Info (10041): Verilog HDL or VHDL info at more1.v(10): inferred latch for \"i\[2\]\"" {  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 10 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "i\[1\] more1.v(10) " "Info (10041): Verilog HDL or VHDL info at more1.v(10): inferred latch for \"i\[1\]\"" {  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 10 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "40 " "Info: Implemented 40 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "13 " "Info: Implemented 13 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "26 " "Info: Implemented 26 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 30 13:00:01 2006 " "Info: Processing ended: Sat Dec 30 13:00:01 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}