more1.fnsim.qmsg

本程序对输入的任意多个二进制数字进行判别（0和1的个数）

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 30 13:00:23 2006 " "Info: Processing started: Sat Dec 30 13:00:23 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off more1 -c more1 --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off more1 -c more1 --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "more1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file more1.v" { { "Info" "ISGN_ENTITY_NAME" "1 more1 " "Info: Found entity 1: more1" {  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "more1 " "Info: Elaborating entity \"more1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 more1.v(17) " "Warning (10230): Verilog HDL assignment warning at more1.v(17): truncated value with size 32 to match size of target (4)" {  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 17 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 more1.v(21) " "Warning (10230): Verilog HDL assignment warning at more1.v(21): truncated value with size 32 to match size of target (1)" {  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 21 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "count more1.v(12) " "Warning (10240): Verilog HDL Always Construct warning at more1.v(12): inferring latch(es) for variable \"count\", which holds its previous value in one or more paths through the always construct" {  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 12 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "count\[4\] more1.v(10) " "Info (10041): Verilog HDL or VHDL info at more1.v(10): inferred latch for \"count\[4\]\"" {  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 10 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "count\[3\] more1.v(10) " "Info (10041): Verilog HDL or VHDL info at more1.v(10): inferred latch for \"count\[3\]\"" {  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 10 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "count\[2\] more1.v(10) " "Info (10041): Verilog HDL or VHDL info at more1.v(10): inferred latch for \"count\[2\]\"" {  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 10 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "count\[1\] more1.v(10) " "Info (10041): Verilog HDL or VHDL info at more1.v(10): inferred latch for \"count\[1\]\"" {  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 10 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "i more1.v(12) " "Warning (10240): Verilog HDL Always Construct warning at more1.v(12): inferring latch(es) for variable \"i\", which holds its previous value in one or more paths through the always construct" {  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 12 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "i\[4\] more1.v(10) " "Info (10041): Verilog HDL or VHDL info at more1.v(10): inferred latch for \"i\[4\]\"" {  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 10 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "i\[3\] more1.v(10) " "Info (10041): Verilog HDL or VHDL info at more1.v(10): inferred latch for \"i\[3\]\"" {  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 10 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "i\[2\] more1.v(10) " "Info (10041): Verilog HDL or VHDL info at more1.v(10): inferred latch for \"i\[2\]\"" {  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 10 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "i\[1\] more1.v(10) " "Info (10041): Verilog HDL or VHDL info at more1.v(10): inferred latch for \"i\[1\]\"" {  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 10 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 19 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../altera/quartus60/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/quartus60/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 266 4 0 } } { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 19 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Info: Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 2 " "Info: Parameter \"LPM_WIDTH\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT NO " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 19 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/addcore.tdf" 94 2 0 } } { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 19 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Info: Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 2 " "Info: Parameter \"LPM_WIDTH\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT NO " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 19 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/addcore.tdf" 120 6 0 } } { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 19 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Info: Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 2 " "Info: Parameter \"LPM_WIDTH\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT NO " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "more1.v" "" { Text "F:/课程/SOC设计/作业/homework/more1/more1.v" 19 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}