diff_io_top_v.sdo

这个verilog代码是一个输入输出经典的例子。大家一起参考。

        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2241:2241:2241) (2241:2241:2241) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[14\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (1616:1616:1616) (1616:1616:1616) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[14\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2241:2241:2241) (2241:2241:2241) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[15\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datac (1419:1419:1419) (1419:1419:1419) )
        (IOPATH datac regin (364:364:364) (364:364:364) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[15\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2241:2241:2241) (2241:2241:2241) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[0\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (1436:1436:1436) (1436:1436:1436) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[0\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2247:2247:2247) (2247:2247:2247) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[1\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (1606:1606:1606) (1606:1606:1606) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[1\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2247:2247:2247) (2247:2247:2247) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[2\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datac (1416:1416:1416) (1416:1416:1416) )
        (IOPATH datac regin (364:364:364) (364:364:364) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[2\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2247:2247:2247) (2247:2247:2247) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[3\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datac (1438:1438:1438) (1438:1438:1438) )
        (IOPATH datac regin (364:364:364) (364:364:364) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[3\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2247:2247:2247) (2247:2247:2247) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[4\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (1614:1614:1614) (1614:1614:1614) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[4\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2247:2247:2247) (2247:2247:2247) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[5\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (1604:1604:1604) (1604:1604:1604) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[5\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2247:2247:2247) (2247:2247:2247) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[6\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (1597:1597:1597) (1597:1597:1597) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[6\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2247:2247:2247) (2247:2247:2247) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[7\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (1397:1397:1397) (1397:1397:1397) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[7\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2247:2247:2247) (2247:2247:2247) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_mac_out_internal" )
    (INSTANCE mult_inst.lpm_mult_component\|auto_generated\|mac_out1.mac_adder )
    (DELAY
      (ABSOLUTE
        (IOPATH dataa dataout (323:323:323) (323:323:323) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_mac_register" )
    (INSTANCE mult_inst.lpm_mult_component\|auto_generated\|mac_out1.dataout_out_reg )
    (DELAY
      (ABSOLUTE
        (PORT clk (2710:2710:2710) (2710:2710:2710) )
        (PORT ena (1080:1080:1080) (1080:1080:1080) )
        (PORT aclr (1072:1072:1072) (1072:1072:1072) )
        (IOPATH (posedge clk) dataout (1033:1033:1033) (1033:1033:1033) )
        (IOPATH (posedge aclr) dataout (1014:1014:1014) (1014:1014:1014) )
      )
    )
    (TIMINGCHECK
      (HOLD data (posedge clk) (75:75:75) )
      (HOLD ena (posedge clk) (75:75:75) )
    )
  )
  (CELL
    (CELLTYPE "stratix_mac_register" )
    (INSTANCE mult_inst.lpm_mult_component\|auto_generated\|mac_mult2\~I.dataa_mac_reg )
    (DELAY
      (ABSOLUTE
        (PORT data[0] (431:431:431) (431:431:431) )
        (PORT data[1] (2480:2480:2480) (2480:2480:2480) )
        (PORT data[2] (2089:2089:2089) (2089:2089:2089) )
        (PORT data[3] (2474:2474:2474) (2474:2474:2474) )
        (PORT data[4] (2335:2335:2335) (2335:2335:2335) )
        (PORT data[5] (2328:2328:2328) (2328:2328:2328) )
        (PORT data[6] (2344:2344:2344) (2344:2344:2344) )
        (PORT data[7] (2377:2377:2377) (2377:2377:2377) )
        (PORT data[8] (2360:2360:2360) (2360:2360:2360) )
        (PORT clk (2776:2776:2776) (2776:2776:2776) )
        (PORT ena (1081:1081:1081) (1081:1081:1081) )
        (PORT aclr (1148:1148:1148) (1148:1148:1148) )
        (IOPATH (posedge clk) dataout (158:158:158) (158:158:158) )
        (IOPATH (posedge aclr) dataout (139:139:139) (139:139:139) )
      )
    )
    (TIMINGCHECK
      (HOLD data (posedge clk) (75:75:75) )
      (HOLD ena (posedge clk) (75:75:75) )
    )
  )
  (CELL
    (CELLTYPE "stratix_mac_register" )
    (INSTANCE mult_inst.lpm_mult_component\|auto_generated\|mac_mult2\~I.datab_mac_reg )
    (DELAY
      (ABSOLUTE
        (PORT data[0] (429:429:429) (429:429:429) )
        (PORT data[1] (2356:2356:2356) (2356:2356:2356) )
        (PORT data[2] (2328:2328:2328) (2328:2328:2328) )
        (PORT data[3] (2300:2300:2300) (2300:2300:2300) )
        (PORT data[4] (2367:2367:2367) (2367:2367:2367) )
        (PORT data[5] (2322:2322:2322) (2322:2322:2322) )
        (PORT data[6] (2340:2340:2340) (2340:2340:2340) )
        (PORT data[7] (2404:2404:2404) (2404:2404:2404) )
        (PORT data[8] (2072:2072:2072) (2072:2072:2072) )
        (PORT clk (2771:2771:2771) (2771:2771:2771) )
        (PORT ena (1076:1076:1076) (1076:1076:1076) )
        (PORT aclr (1143:1143:1143) (1143:1143:1143) )
        (IOPATH (posedge clk) dataout (158:158:158) (158:158:158) )
        (IOPATH (posedge aclr) dataout (139:139:139) (139:139:139) )
      )
    )
    (TIMINGCHECK
      (HOLD data (posedge clk) (75:75:75) )
      (HOLD ena (posedge clk) (75:75:75) )
    )
  )
  (CELL
    (CELLTYPE "stratix_mac_mult_internal" )
    (INSTANCE mult_inst.lpm_mult_component\|auto_generated\|mac_mult2\~I.mac_multiply )
    (DELAY
      (ABSOLUTE
        (IOPATH dataa dataout (2982:2982:2982) (2982:2982:2982) )
        (IOPATH datab dataout (3183:3183:3183) (3183:3183:3183) )
        (IOPATH dataa scanouta (2000:2000:2000) (2000:2000:2000) )
        (IOPATH datab scanoutb (2000:2000:2000) (2000:2000:2000) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_mac_register" )
    (INSTANCE mult_inst.lpm_mult_component\|auto_generated\|mac_mult2\~I.dataout_mac_reg )
    (DELAY
      (ABSOLUTE
        (PORT clk (2710:2710:2710) (2710:2710:2710) )
        (PORT ena (1080:1080:1080) (1080:1080:1080) )
        (PORT aclr (1072:1072:1072) (1072:1072:1072) )
        (IOPATH (posedge clk) dataout (319:319:319) (319:319:319) )
        (IOPATH (posedge aclr) dataout (300:300:300) (300:300:300) )
      )
    )
    (TIMINGCHECK
      (HOLD data (posedge clk) (75:75:75) )
      (HOLD ena (posedge clk) (75:75:75) )
    )
  )
)