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📄 diff_io_top_v.sdo

📁 这个verilog代码是一个输入输出经典的例子。大家一起参考。
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1234 
        (IOPATH (posedge clk) dataout[7] (393:393:393) (393:393:393) )
      )
    )
    (TIMINGCHECK
      (SETUP datain[0] (posedge clk) (80:80:80) )
      (HOLD datain[0] (posedge clk) (68:68:68) )
      (SETUP datain[1] (posedge clk) (80:80:80) )
      (HOLD datain[1] (posedge clk) (68:68:68) )
      (SETUP datain[2] (posedge clk) (80:80:80) )
      (HOLD datain[2] (posedge clk) (68:68:68) )
      (SETUP datain[3] (posedge clk) (80:80:80) )
      (HOLD datain[3] (posedge clk) (68:68:68) )
      (SETUP datain[4] (posedge clk) (80:80:80) )
      (HOLD datain[4] (posedge clk) (68:68:68) )
      (SETUP datain[5] (posedge clk) (80:80:80) )
      (HOLD datain[5] (posedge clk) (68:68:68) )
      (SETUP datain[6] (posedge clk) (80:80:80) )
      (HOLD datain[6] (posedge clk) (68:68:68) )
      (SETUP datain[7] (posedge clk) (80:80:80) )
      (HOLD datain[7] (posedge clk) (68:68:68) )
    )
  )
  (CELL
    (CELLTYPE "dffe" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|tx\[1\].txload0_reg )
    (DELAY
      (ABSOLUTE
        (PORT D (1288:1288:1288) (1288:1288:1288) )
        (PORT CLK (1269:1269:1269) (1269:1269:1269) )
        (IOPATH (posedge CLK) Q (171:171:171) (171:171:171) )
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (80:80:80) )
      (HOLD D (posedge CLK) (68:68:68) )
    )
  )
  (CELL
    (CELLTYPE "dffe" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|tx\[1\].txload1_reg )
    (DELAY
      (ABSOLUTE
        (PORT D (50:50:50) (50:50:50) )
        (PORT CLK (1269:1269:1269) (1269:1269:1269) )
        (IOPATH (posedge CLK) Q (171:171:171) (171:171:171) )
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (80:80:80) )
      (HOLD D (posedge CLK) (68:68:68) )
    )
  )
  (CELL
    (CELLTYPE "dffe" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|tx\[1\].txload2_reg )
    (DELAY
      (ABSOLUTE
        (PORT D (50:50:50) (50:50:50) )
        (PORT CLK (1269:1269:1269) (1269:1269:1269) )
        (IOPATH (posedge CLK) Q (171:171:171) (171:171:171) )
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (80:80:80) )
      (HOLD D (posedge CLK) (68:68:68) )
    )
  )
  (CELL
    (CELLTYPE "stratix_lvds_tx_parallel_register" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|tx\[0\].input_reg )
    (DELAY
      (ABSOLUTE
        (PORT clk (1269:1269:1269) (1269:1269:1269) )
        (PORT enable (50:50:50) (50:50:50) )
        (PORT datain[0] (1554:1554:1554) (1554:1554:1554) )
        (PORT datain[1] (1547:1547:1547) (1547:1547:1547) )
        (PORT datain[2] (1542:1542:1542) (1542:1542:1542) )
        (PORT datain[3] (1548:1548:1548) (1548:1548:1548) )
        (PORT datain[4] (1551:1551:1551) (1551:1551:1551) )
        (PORT datain[5] (1546:1546:1546) (1546:1546:1546) )
        (PORT datain[6] (1546:1546:1546) (1546:1546:1546) )
        (PORT datain[7] (1544:1544:1544) (1544:1544:1544) )
        (IOPATH (posedge clk) dataout[0] (393:393:393) (393:393:393) )
        (IOPATH (posedge clk) dataout[1] (393:393:393) (393:393:393) )
        (IOPATH (posedge clk) dataout[2] (393:393:393) (393:393:393) )
        (IOPATH (posedge clk) dataout[3] (393:393:393) (393:393:393) )
        (IOPATH (posedge clk) dataout[4] (393:393:393) (393:393:393) )
        (IOPATH (posedge clk) dataout[5] (393:393:393) (393:393:393) )
        (IOPATH (posedge clk) dataout[6] (393:393:393) (393:393:393) )
        (IOPATH (posedge clk) dataout[7] (393:393:393) (393:393:393) )
      )
    )
    (TIMINGCHECK
      (SETUP datain[0] (posedge clk) (80:80:80) )
      (HOLD datain[0] (posedge clk) (68:68:68) )
      (SETUP datain[1] (posedge clk) (80:80:80) )
      (HOLD datain[1] (posedge clk) (68:68:68) )
      (SETUP datain[2] (posedge clk) (80:80:80) )
      (HOLD datain[2] (posedge clk) (68:68:68) )
      (SETUP datain[3] (posedge clk) (80:80:80) )
      (HOLD datain[3] (posedge clk) (68:68:68) )
      (SETUP datain[4] (posedge clk) (80:80:80) )
      (HOLD datain[4] (posedge clk) (68:68:68) )
      (SETUP datain[5] (posedge clk) (80:80:80) )
      (HOLD datain[5] (posedge clk) (68:68:68) )
      (SETUP datain[6] (posedge clk) (80:80:80) )
      (HOLD datain[6] (posedge clk) (68:68:68) )
      (SETUP datain[7] (posedge clk) (80:80:80) )
      (HOLD datain[7] (posedge clk) (68:68:68) )
    )
  )
  (CELL
    (CELLTYPE "dffe" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|tx\[0\].txload0_reg )
    (DELAY
      (ABSOLUTE
        (PORT D (1288:1288:1288) (1288:1288:1288) )
        (PORT CLK (1269:1269:1269) (1269:1269:1269) )
        (IOPATH (posedge CLK) Q (171:171:171) (171:171:171) )
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (80:80:80) )
      (HOLD D (posedge CLK) (68:68:68) )
    )
  )
  (CELL
    (CELLTYPE "dffe" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|tx\[0\].txload1_reg )
    (DELAY
      (ABSOLUTE
        (PORT D (50:50:50) (50:50:50) )
        (PORT CLK (1269:1269:1269) (1269:1269:1269) )
        (IOPATH (posedge CLK) Q (171:171:171) (171:171:171) )
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (80:80:80) )
      (HOLD D (posedge CLK) (68:68:68) )
    )
  )
  (CELL
    (CELLTYPE "dffe" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|tx\[0\].txload2_reg )
    (DELAY
      (ABSOLUTE
        (PORT D (50:50:50) (50:50:50) )
        (PORT CLK (1269:1269:1269) (1269:1269:1269) )
        (IOPATH (posedge CLK) Q (171:171:171) (171:171:171) )
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (80:80:80) )
      (HOLD D (posedge CLK) (68:68:68) )
    )
  )
  (CELL
    (CELLTYPE "stratix_lvds_tx_parallel_register" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|outclock_tx.input_reg )
    (DELAY
      (ABSOLUTE
        (PORT clk (1269:1269:1269) (1269:1269:1269) )
        (PORT enable (50:50:50) (50:50:50) )
        (IOPATH (posedge clk) dataout[0] (393:393:393) (393:393:393) )
        (IOPATH (posedge clk) dataout[1] (393:393:393) (393:393:393) )
        (IOPATH (posedge clk) dataout[2] (393:393:393) (393:393:393) )
        (IOPATH (posedge clk) dataout[3] (393:393:393) (393:393:393) )
        (IOPATH (posedge clk) dataout[4] (393:393:393) (393:393:393) )
        (IOPATH (posedge clk) dataout[5] (393:393:393) (393:393:393) )
        (IOPATH (posedge clk) dataout[6] (393:393:393) (393:393:393) )
        (IOPATH (posedge clk) dataout[7] (393:393:393) (393:393:393) )
      )
    )
    (TIMINGCHECK
      (SETUP datain[0] (posedge clk) (80:80:80) )
      (HOLD datain[0] (posedge clk) (68:68:68) )
      (SETUP datain[1] (posedge clk) (80:80:80) )
      (HOLD datain[1] (posedge clk) (68:68:68) )
      (SETUP datain[2] (posedge clk) (80:80:80) )
      (HOLD datain[2] (posedge clk) (68:68:68) )
      (SETUP datain[3] (posedge clk) (80:80:80) )
      (HOLD datain[3] (posedge clk) (68:68:68) )
      (SETUP datain[4] (posedge clk) (80:80:80) )
      (HOLD datain[4] (posedge clk) (68:68:68) )
      (SETUP datain[5] (posedge clk) (80:80:80) )
      (HOLD datain[5] (posedge clk) (68:68:68) )
      (SETUP datain[6] (posedge clk) (80:80:80) )
      (HOLD datain[6] (posedge clk) (68:68:68) )
      (SETUP datain[7] (posedge clk) (80:80:80) )
      (HOLD datain[7] (posedge clk) (68:68:68) )
    )
  )
  (CELL
    (CELLTYPE "dffe" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|outclock_tx.txload0_reg )
    (DELAY
      (ABSOLUTE
        (PORT D (1288:1288:1288) (1288:1288:1288) )
        (PORT CLK (1269:1269:1269) (1269:1269:1269) )
        (IOPATH (posedge CLK) Q (171:171:171) (171:171:171) )
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (80:80:80) )
      (HOLD D (posedge CLK) (68:68:68) )
    )
  )
  (CELL
    (CELLTYPE "dffe" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|outclock_tx.txload1_reg )
    (DELAY
      (ABSOLUTE
        (PORT D (50:50:50) (50:50:50) )
        (PORT CLK (1269:1269:1269) (1269:1269:1269) )
        (IOPATH (posedge CLK) Q (171:171:171) (171:171:171) )
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (80:80:80) )
      (HOLD D (posedge CLK) (68:68:68) )
    )
  )
  (CELL
    (CELLTYPE "dffe" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|outclock_tx.txload2_reg )
    (DELAY
      (ABSOLUTE
        (PORT D (50:50:50) (50:50:50) )
        (PORT CLK (1269:1269:1269) (1269:1269:1269) )
        (IOPATH (posedge CLK) Q (171:171:171) (171:171:171) )
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (80:80:80) )
      (HOLD D (posedge CLK) (68:68:68) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[8\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (1602:1602:1602) (1602:1602:1602) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[8\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2241:2241:2241) (2241:2241:2241) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[9\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (1614:1614:1614) (1614:1614:1614) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[9\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2241:2241:2241) (2241:2241:2241) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[10\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (1611:1611:1611) (1611:1611:1611) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[10\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2241:2241:2241) (2241:2241:2241) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[11\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (1607:1607:1607) (1607:1607:1607) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[11\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2241:2241:2241) (2241:2241:2241) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[12\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (1603:1603:1603) (1603:1603:1603) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[12\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2241:2241:2241) (2241:2241:2241) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[13\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (1615:1615:1615) (1615:1615:1615) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|txreg\[13\]\~I.lereg )
    (DELAY
      (ABSOLUTE
1234

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