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📄 diff_io_top_v.sdo

📁 这个verilog代码是一个输入输出经典的例子。大家一起参考。
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1234 
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[5\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (417:417:417) (417:417:417) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[5\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2222:2222:2222) (2222:2222:2222) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[4\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (418:418:418) (418:418:418) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[4\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2222:2222:2222) (2222:2222:2222) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[3\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (506:506:506) (506:506:506) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[3\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2222:2222:2222) (2222:2222:2222) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[2\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (840:840:840) (840:840:840) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[2\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2222:2222:2222) (2222:2222:2222) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[1\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (503:503:503) (503:503:503) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[1\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2222:2222:2222) (2222:2222:2222) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[0\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (859:859:859) (859:859:859) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[0\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2222:2222:2222) (2222:2222:2222) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|pll\~0_I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (1063:1063:1063) (1063:1063:1063) )
        (IOPATH datad combout (87:87:87) (87:87:87) )
      )
    )
  )
  (CELL
    (CELLTYPE "dffe" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rx\[1\]\~I.rxload0_reg )
    (DELAY
      (ABSOLUTE
        (PORT D (1353:1353:1353) (1353:1353:1353) )
        (PORT CLK (1433:1433:1433) (1433:1433:1433) )
        (IOPATH (posedge CLK) Q (171:171:171) (171:171:171) )
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (80:80:80) )
      (HOLD D (posedge CLK) (68:68:68) )
    )
  )
  (CELL
    (CELLTYPE "dffe" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rx\[1\]\~I.rxload1_reg )
    (DELAY
      (ABSOLUTE
        (PORT D (50:50:50) (50:50:50) )
        (PORT CLK (1433:1433:1433) (1433:1433:1433) )
        (IOPATH (posedge CLK) Q (171:171:171) (171:171:171) )
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (80:80:80) )
      (HOLD D (posedge CLK) (68:68:68) )
    )
  )
  (CELL
    (CELLTYPE "dffe" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rx\[1\]\~I.rxload2_reg )
    (DELAY
      (ABSOLUTE
        (PORT D (50:50:50) (50:50:50) )
        (PORT CLK (1433:1433:1433) (1433:1433:1433) )
        (IOPATH (posedge CLK) Q (171:171:171) (171:171:171) )
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (80:80:80) )
      (HOLD D (posedge CLK) (68:68:68) )
    )
  )
  (CELL
    (CELLTYPE "stratix_lvds_rx_parallel_register" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rx\[1\]\~I.load_reg )
    (DELAY
      (ABSOLUTE
        (PORT clk (1433:1433:1433) (1433:1433:1433) )
        (PORT enable (50:50:50) (50:50:50) )
        (PORT datain[0] (222:222:222) (222:222:222) )
        (PORT datain[1] (222:222:222) (222:222:222) )
        (PORT datain[2] (222:222:222) (222:222:222) )
        (PORT datain[3] (222:222:222) (222:222:222) )
        (PORT datain[4] (222:222:222) (222:222:222) )
        (PORT datain[5] (222:222:222) (222:222:222) )
        (PORT datain[6] (222:222:222) (222:222:222) )
        (PORT datain[7] (222:222:222) (222:222:222) )
        (IOPATH (posedge clk) dataout[0] (171:171:171) (171:171:171) )
        (IOPATH (posedge clk) dataout[1] (171:171:171) (171:171:171) )
        (IOPATH (posedge clk) dataout[2] (171:171:171) (171:171:171) )
        (IOPATH (posedge clk) dataout[3] (171:171:171) (171:171:171) )
        (IOPATH (posedge clk) dataout[4] (171:171:171) (171:171:171) )
        (IOPATH (posedge clk) dataout[5] (171:171:171) (171:171:171) )
        (IOPATH (posedge clk) dataout[6] (171:171:171) (171:171:171) )
        (IOPATH (posedge clk) dataout[7] (171:171:171) (171:171:171) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lvds_rx_parallel_register" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rx\[1\]\~I.output_reg )
    (DELAY
      (ABSOLUTE
        (PORT clk (1433:1433:1433) (1433:1433:1433) )
        (PORT enable (1574:1574:1574) (1574:1574:1574) )
        (PORT datain[0] (50:50:50) (50:50:50) )
        (PORT datain[1] (50:50:50) (50:50:50) )
        (PORT datain[2] (50:50:50) (50:50:50) )
        (PORT datain[3] (50:50:50) (50:50:50) )
        (PORT datain[4] (50:50:50) (50:50:50) )
        (PORT datain[5] (50:50:50) (50:50:50) )
        (PORT datain[6] (50:50:50) (50:50:50) )
        (PORT datain[7] (50:50:50) (50:50:50) )
        (IOPATH (posedge clk) dataout[0] (558:558:558) (558:558:558) )
        (IOPATH (posedge clk) dataout[1] (558:558:558) (558:558:558) )
        (IOPATH (posedge clk) dataout[2] (558:558:558) (558:558:558) )
        (IOPATH (posedge clk) dataout[3] (558:558:558) (558:558:558) )
        (IOPATH (posedge clk) dataout[4] (558:558:558) (558:558:558) )
        (IOPATH (posedge clk) dataout[5] (558:558:558) (558:558:558) )
        (IOPATH (posedge clk) dataout[6] (558:558:558) (558:558:558) )
        (IOPATH (posedge clk) dataout[7] (558:558:558) (558:558:558) )
      )
    )
  )
  (CELL
    (CELLTYPE "dffe" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rx\[0\]\~I.rxload0_reg )
    (DELAY
      (ABSOLUTE
        (PORT D (1353:1353:1353) (1353:1353:1353) )
        (PORT CLK (1433:1433:1433) (1433:1433:1433) )
        (IOPATH (posedge CLK) Q (171:171:171) (171:171:171) )
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (80:80:80) )
      (HOLD D (posedge CLK) (68:68:68) )
    )
  )
  (CELL
    (CELLTYPE "dffe" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rx\[0\]\~I.rxload1_reg )
    (DELAY
      (ABSOLUTE
        (PORT D (50:50:50) (50:50:50) )
        (PORT CLK (1433:1433:1433) (1433:1433:1433) )
        (IOPATH (posedge CLK) Q (171:171:171) (171:171:171) )
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (80:80:80) )
      (HOLD D (posedge CLK) (68:68:68) )
    )
  )
  (CELL
    (CELLTYPE "dffe" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rx\[0\]\~I.rxload2_reg )
    (DELAY
      (ABSOLUTE
        (PORT D (50:50:50) (50:50:50) )
        (PORT CLK (1433:1433:1433) (1433:1433:1433) )
        (IOPATH (posedge CLK) Q (171:171:171) (171:171:171) )
      )
    )
    (TIMINGCHECK
      (SETUP D (posedge CLK) (80:80:80) )
      (HOLD D (posedge CLK) (68:68:68) )
    )
  )
  (CELL
    (CELLTYPE "stratix_lvds_rx_parallel_register" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rx\[0\]\~I.load_reg )
    (DELAY
      (ABSOLUTE
        (PORT clk (1433:1433:1433) (1433:1433:1433) )
        (PORT enable (50:50:50) (50:50:50) )
        (PORT datain[0] (222:222:222) (222:222:222) )
        (PORT datain[1] (222:222:222) (222:222:222) )
        (PORT datain[2] (222:222:222) (222:222:222) )
        (PORT datain[3] (222:222:222) (222:222:222) )
        (PORT datain[4] (222:222:222) (222:222:222) )
        (PORT datain[5] (222:222:222) (222:222:222) )
        (PORT datain[6] (222:222:222) (222:222:222) )
        (PORT datain[7] (222:222:222) (222:222:222) )
        (IOPATH (posedge clk) dataout[0] (171:171:171) (171:171:171) )
        (IOPATH (posedge clk) dataout[1] (171:171:171) (171:171:171) )
        (IOPATH (posedge clk) dataout[2] (171:171:171) (171:171:171) )
        (IOPATH (posedge clk) dataout[3] (171:171:171) (171:171:171) )
        (IOPATH (posedge clk) dataout[4] (171:171:171) (171:171:171) )
        (IOPATH (posedge clk) dataout[5] (171:171:171) (171:171:171) )
        (IOPATH (posedge clk) dataout[6] (171:171:171) (171:171:171) )
        (IOPATH (posedge clk) dataout[7] (171:171:171) (171:171:171) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lvds_rx_parallel_register" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rx\[0\]\~I.output_reg )
    (DELAY
      (ABSOLUTE
        (PORT clk (1433:1433:1433) (1433:1433:1433) )
        (PORT enable (1574:1574:1574) (1574:1574:1574) )
        (PORT datain[0] (50:50:50) (50:50:50) )
        (PORT datain[1] (50:50:50) (50:50:50) )
        (PORT datain[2] (50:50:50) (50:50:50) )
        (PORT datain[3] (50:50:50) (50:50:50) )
        (PORT datain[4] (50:50:50) (50:50:50) )
        (PORT datain[5] (50:50:50) (50:50:50) )
        (PORT datain[6] (50:50:50) (50:50:50) )
        (PORT datain[7] (50:50:50) (50:50:50) )
        (IOPATH (posedge clk) dataout[0] (558:558:558) (558:558:558) )
        (IOPATH (posedge clk) dataout[1] (558:558:558) (558:558:558) )
        (IOPATH (posedge clk) dataout[2] (558:558:558) (558:558:558) )
        (IOPATH (posedge clk) dataout[3] (558:558:558) (558:558:558) )
        (IOPATH (posedge clk) dataout[4] (558:558:558) (558:558:558) )
        (IOPATH (posedge clk) dataout[5] (558:558:558) (558:558:558) )
        (IOPATH (posedge clk) dataout[6] (558:558:558) (558:558:558) )
        (IOPATH (posedge clk) dataout[7] (558:558:558) (558:558:558) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lvds_tx_parallel_register" )
    (INSTANCE lvds_tx_inst.altlvds_tx_component\|tx\[1\].input_reg )
    (DELAY
      (ABSOLUTE
        (PORT clk (1269:1269:1269) (1269:1269:1269) )
        (PORT enable (50:50:50) (50:50:50) )
        (PORT datain[0] (1549:1549:1549) (1549:1549:1549) )
        (PORT datain[1] (1557:1557:1557) (1557:1557:1557) )
        (PORT datain[2] (1541:1541:1541) (1541:1541:1541) )
        (PORT datain[3] (1546:1546:1546) (1546:1546:1546) )
        (PORT datain[4] (1549:1549:1549) (1549:1549:1549) )
        (PORT datain[5] (1546:1546:1546) (1546:1546:1546) )
        (PORT datain[6] (1557:1557:1557) (1557:1557:1557) )
        (PORT datain[7] (1546:1546:1546) (1546:1546:1546) )
        (IOPATH (posedge clk) dataout[0] (393:393:393) (393:393:393) )
        (IOPATH (posedge clk) dataout[1] (393:393:393) (393:393:393) )
        (IOPATH (posedge clk) dataout[2] (393:393:393) (393:393:393) )
        (IOPATH (posedge clk) dataout[3] (393:393:393) (393:393:393) )
        (IOPATH (posedge clk) dataout[4] (393:393:393) (393:393:393) )
        (IOPATH (posedge clk) dataout[5] (393:393:393) (393:393:393) )
        (IOPATH (posedge clk) dataout[6] (393:393:393) (393:393:393) )
1234

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