diff_io_top_v.sdo

这个verilog代码是一个输入输出经典的例子。大家一起参考。

// Copyright (C) 1991-2002 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.


// 
// Device: Altera EP1S60F1508C6 Package FBGA1508
// 

// 
// This SDF file should be used for MODELSIM (VERILOG HDL OUTPUT FROM QUARTUS II) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "Diff_io_top")
  (DATE "01/23/2003 15:19:15")
  (VENDOR "Altera")
  (PROGRAM "Quartus II")
  (VERSION "Version 2.2 Build 147 12/02/2002 SJ Full Version")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE rx_data_align\~I.inst1 )
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1093:1093:1093) (1093:1093:1093) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE rx_in\[0\]\~I.inst1 )
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1121:1121:1121) (1121:1121:1121) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE rx_in\[1\]\~I.inst1 )
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1121:1121:1121) (1121:1121:1121) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE rx_inclock\~I.inst1 )
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (673:673:673) (673:673:673) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE rx_locked\~I.inst1 )
    (DELAY
      (ABSOLUTE
        (PORT datain (2320:2320:2320) (2320:2320:2320) )
        (IOPATH datain padio (2529:2529:2529) (2529:2529:2529) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE tx_out\[1\]\~I.inst1 )
    (DELAY
      (ABSOLUTE
        (IOPATH datain padio (1117:1117:1117) (1117:1117:1117) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE tx_out\[0\]\~I.inst1 )
    (DELAY
      (ABSOLUTE
        (IOPATH datain padio (1117:1117:1117) (1117:1117:1117) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE tx_outclock\~I.inst1 )
    (DELAY
      (ABSOLUTE
        (IOPATH datain padio (1117:1117:1117) (1117:1117:1117) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_pll" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|pll\~I )
    (DELAY
      (ABSOLUTE
        (PORT comparator (2506:2506:2506) (2506:2506:2506) )
        (PORT inclk[0] (649:649:649) (649:649:649) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[15\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (656:656:656) (656:656:656) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[15\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2211:2211:2211) (2211:2211:2211) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[14\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (659:659:659) (659:659:659) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[14\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2211:2211:2211) (2211:2211:2211) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[13\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (414:414:414) (414:414:414) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[13\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2211:2211:2211) (2211:2211:2211) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[12\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (414:414:414) (414:414:414) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[12\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2211:2211:2211) (2211:2211:2211) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[11\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (506:506:506) (506:506:506) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[11\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2211:2211:2211) (2211:2211:2211) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[10\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (841:841:841) (841:841:841) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[10\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2211:2211:2211) (2211:2211:2211) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[9\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (507:507:507) (507:507:507) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[9\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2211:2211:2211) (2211:2211:2211) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[8\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (835:835:835) (835:835:835) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[8\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2211:2211:2211) (2211:2211:2211) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[7\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (655:655:655) (655:655:655) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[7\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2222:2222:2222) (2222:2222:2222) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[6\]\~I.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT datad (659:659:659) (659:659:659) )
        (IOPATH datad regin (235:235:235) (235:235:235) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register" )
    (INSTANCE lvds_rx_inst.altlvds_rx_component\|rxreg\[6\]\~I.lereg )
    (DELAY
      (ABSOLUTE
        (PORT aclr (668:668:668) (668:668:668) )
        (PORT clk (2222:2222:2222) (2222:2222:2222) )
        (IOPATH (posedge clk) regout (176:176:176) (176:176:176) )
        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10) )
      (HOLD datain (posedge clk) (100:100:100) )
    )
  )