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📄 diff_io_top.vo

📁 这个verilog代码是一个输入输出经典的例子。大家一起参考。
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	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(result_14),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\altlvds_tx_component|txreg[14] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_tx_component|txreg[14]~I .operation_mode = "normal";
defparam \altlvds_tx_component|txreg[14]~I .synch_mode = "off";
defparam \altlvds_tx_component|txreg[14]~I .register_cascade_mode = "off";
defparam \altlvds_tx_component|txreg[14]~I .sum_lutc_input = "datac";
defparam \altlvds_tx_component|txreg[14]~I .lut_mask = "FF00";
defparam \altlvds_tx_component|txreg[14]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X3_Y61_N6
stratix_lcell \altlvds_tx_component|txreg[15]~I (
// Equation(s):
// \altlvds_tx_component|txreg[15]  = DFFEA(result, GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(result_15),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\altlvds_tx_component|txreg[15] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_tx_component|txreg[15]~I .operation_mode = "normal";
defparam \altlvds_tx_component|txreg[15]~I .synch_mode = "off";
defparam \altlvds_tx_component|txreg[15]~I .register_cascade_mode = "off";
defparam \altlvds_tx_component|txreg[15]~I .sum_lutc_input = "datac";
defparam \altlvds_tx_component|txreg[15]~I .lut_mask = "F0F0";
defparam \altlvds_tx_component|txreg[15]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X3_Y60_N7
stratix_lcell \altlvds_tx_component|txreg[0]~I (
// Equation(s):
// \altlvds_tx_component|txreg[0]  = DFFEA(result, GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(result_0),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\altlvds_tx_component|txreg[0] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_tx_component|txreg[0]~I .operation_mode = "normal";
defparam \altlvds_tx_component|txreg[0]~I .synch_mode = "off";
defparam \altlvds_tx_component|txreg[0]~I .register_cascade_mode = "off";
defparam \altlvds_tx_component|txreg[0]~I .sum_lutc_input = "datac";
defparam \altlvds_tx_component|txreg[0]~I .lut_mask = "FF00";
defparam \altlvds_tx_component|txreg[0]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X3_Y60_N4
stratix_lcell \altlvds_tx_component|txreg[1]~I (
// Equation(s):
// \altlvds_tx_component|txreg[1]  = DFFEA(result, GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(result_1),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\altlvds_tx_component|txreg[1] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_tx_component|txreg[1]~I .operation_mode = "normal";
defparam \altlvds_tx_component|txreg[1]~I .synch_mode = "off";
defparam \altlvds_tx_component|txreg[1]~I .register_cascade_mode = "off";
defparam \altlvds_tx_component|txreg[1]~I .sum_lutc_input = "datac";
defparam \altlvds_tx_component|txreg[1]~I .lut_mask = "FF00";
defparam \altlvds_tx_component|txreg[1]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X3_Y60_N3
stratix_lcell \altlvds_tx_component|txreg[2]~I (
// Equation(s):
// \altlvds_tx_component|txreg[2]  = DFFEA(result, GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(result_2),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\altlvds_tx_component|txreg[2] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_tx_component|txreg[2]~I .operation_mode = "normal";
defparam \altlvds_tx_component|txreg[2]~I .synch_mode = "off";
defparam \altlvds_tx_component|txreg[2]~I .register_cascade_mode = "off";
defparam \altlvds_tx_component|txreg[2]~I .sum_lutc_input = "datac";
defparam \altlvds_tx_component|txreg[2]~I .lut_mask = "F0F0";
defparam \altlvds_tx_component|txreg[2]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X3_Y60_N9
stratix_lcell \altlvds_tx_component|txreg[3]~I (
// Equation(s):
// \altlvds_tx_component|txreg[3]  = DFFEA(result, GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(result_3),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\altlvds_tx_component|txreg[3] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_tx_component|txreg[3]~I .operation_mode = "normal";
defparam \altlvds_tx_component|txreg[3]~I .synch_mode = "off";
defparam \altlvds_tx_component|txreg[3]~I .register_cascade_mode = "off";
defparam \altlvds_tx_component|txreg[3]~I .sum_lutc_input = "datac";
defparam \altlvds_tx_component|txreg[3]~I .lut_mask = "F0F0";
defparam \altlvds_tx_component|txreg[3]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X3_Y60_N8
stratix_lcell \altlvds_tx_component|txreg[4]~I (
// Equation(s):
// \altlvds_tx_component|txreg[4]  = DFFEA(result, GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(result_4),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\altlvds_tx_component|txreg[4] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_tx_component|txreg[4]~I .operation_mode = "normal";
defparam \altlvds_tx_component|txreg[4]~I .synch_mode = "off";
defparam \altlvds_tx_component|txreg[4]~I .register_cascade_mode = "off";
defparam \altlvds_tx_component|txreg[4]~I .sum_lutc_input = "datac";
defparam \altlvds_tx_component|txreg[4]~I .lut_mask = "FF00";
defparam \altlvds_tx_component|txreg[4]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X3_Y60_N6
stratix_lcell \altlvds_tx_component|txreg[5]~I (
// Equation(s):
// \altlvds_tx_component|txreg[5]  = DFFEA(result, GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(result_5),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\altlvds_tx_component|txreg[5] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_tx_component|txreg[5]~I .operation_mode = "normal";
defparam \altlvds_tx_component|txreg[5]~I .synch_mode = "off";
defparam \altlvds_tx_component|txreg[5]~I .register_cascade_mode = "off";
defparam \altlvds_tx_component|txreg[5]~I .sum_lutc_input = "datac";
defparam \altlvds_tx_component|txreg[5]~I .lut_mask = "FF00";
defparam \altlvds_tx_component|txreg[5]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X3_Y60_N2
stratix_lcell \altlvds_tx_component|txreg[6]~I (
// Equation(s):
// \altlvds_tx_component|txreg[6]  = DFFEA(result, GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(result_6),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\altlvds_tx_component|txreg[6] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_tx_component|txreg[6]~I .operation_mode = "normal";
defparam \altlvds_tx_component|txreg[6]~I .synch_mode = "off";
defparam \altlvds_tx_component|txreg[6]~I .register_cascade_mode = "off";
defparam \altlvds_tx_component|txreg[6]~I .sum_lutc_input = "datac";
defparam \altlvds_tx_component|txreg[6]~I .lut_mask = "FF00";
defparam \altlvds_tx_component|txreg[6]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X3_Y60_N5
stratix_lcell \altlvds_tx_component|txreg[7]~I (
// Equation(s):
// \altlvds_tx_component|txreg[7]  = DFFEA(result, GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(result_7),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\altlvds_tx_component|txreg[7] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_tx_component|txreg[7]~I .operation_mode = "normal";
defparam \altlvds_tx_component|txreg[7]~I .synch_mode = "off";
defparam \altlvds_tx_component|txreg[7]~I .register_cascade_mode = "off";
defparam \altlvds_tx_component|txreg[7]~I .sum_lutc_input = "datac";
defparam \altlvds_tx_component|txreg[7]~I .lut_mask = "FF00";
defparam \altlvds_tx_component|txreg[7]~I .output_mode = "reg_only";
// synopsys translate_on

endmodule

module 	mult (
	clock,
	datab,
	dataa,
	devclrn,
	devpor,
	devoe,
	result);
input 	clock;
input 	[7:0] datab;
input 	[7:0] dataa;
input 	devclrn;
input 	devpor;
input 	devoe;
output 	[15:0] result;

supply0 gnd;
supply1 vcc;

wire \lpm_mult_component|auto_generated|mac_mult2~SCANOUTA0 ;
wire \lpm_mult_component|auto_generated|mac_mult2~SCANOUTA1 ;
wire \lpm_mult_component|auto_generated|mac_mult2~SCANOUTA2 ;
wire \lpm_mult_component|auto_generated|mac_mult2~SCANOUTA3 ;
wire \lpm_mult_component|auto_generated|mac_mult2~SCANOUTA4 ;
wire \lpm_mult_component|auto_generated|mac_mult2~SCANOUTA5 ;
wire \lpm_mult_component|auto_generated|mac_mult2~SCANOUTA6 ;
wire \lpm_mult_component|auto_generated|mac_mult2~SCANOUTA7 ;
wire \lpm_mult_component|auto_generated|mac_mult2~SCANOUTB0 ;
wire \lpm_mult_component|auto_generated|mac_mult2~SCANOUTB1 ;
wire \lpm_mult_component|auto_generated|mac_mult2~SCANOUTB2 ;
wire \lpm_mult_component|auto_generated|mac_mult2~SCANOUTB3 ;
wire \lpm_mult_component|auto_generated|mac_mult2~SCANOUTB4 ;
wire \lpm_mult_component|auto_generated|mac_mult2~SCANOUTB5 ;
wire \lpm_mult_component|auto_generated|mac_mult2~SCANOUTB6 ;
wire \lpm_mult_component|auto_generated|mac_mult2~SCANOUTB7 ;
wire \lpm_mult_component|auto_generated|mac_mult2~2 ;
wire \lpm_mult_component|auto_generated|mac_mult2~3 ;
wire \lpm_mult_component|auto_generated|mac_out1~OVERFLOW ;
wire \lpm_mult_component|auto_generated|mac_out1~0 ;
wire \lpm_mult_component|auto_generated|mac_out1~1 ;
wire \lpm_mult_component|auto_generat
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