diff_io_top.vo

这个verilog代码是一个输入输出经典的例子。大家一起参考。

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\altlvds_rx_component|pll~LOCKED ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(rx_locked),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_rx_component|pll~0_I .operation_mode = "normal";
defparam \altlvds_rx_component|pll~0_I .synch_mode = "off";
defparam \altlvds_rx_component|pll~0_I .register_cascade_mode = "off";
defparam \altlvds_rx_component|pll~0_I .sum_lutc_input = "datac";
defparam \altlvds_rx_component|pll~0_I .lut_mask = "00FF";
defparam \altlvds_rx_component|pll~0_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at SERDESRX_X0_Y48_N4
stratix_lvds_receiver \altlvds_rx_component|rx[1]~I (
	.datain(rx_in[1]),
	.clk0(pll1),
	.enable0(\altlvds_rx_component|pll~ENAOUT0 ),
	.enable1(pll),
	.devclrn(devclrn),
	.devpor(devpor),
	.dataout(\ww_altlvds_rx_component|rx[1]~I_dataout ));
// synopsys translate_off
defparam \altlvds_rx_component|rx[1]~I .channel_width = 8;
defparam \altlvds_rx_component|rx[1]~I .use_enable1 = "true";
// synopsys translate_on

// atom is at SERDESRX_X0_Y49_N4
stratix_lvds_receiver \altlvds_rx_component|rx[0]~I (
	.datain(rx_in[0]),
	.clk0(pll1),
	.enable0(\altlvds_rx_component|pll~ENAOUT0 ),
	.enable1(pll),
	.devclrn(devclrn),
	.devpor(devpor),
	.dataout(\ww_altlvds_rx_component|rx[0]~I_dataout ));
// synopsys translate_off
defparam \altlvds_rx_component|rx[0]~I .channel_width = 8;
defparam \altlvds_rx_component|rx[0]~I .use_enable1 = "true";
// synopsys translate_on

endmodule

module 	lvds_tx (
	pll,
	pll1,
	pll2,
	rx_outclock,
	result_0,
	result_1,
	result_2,
	result_3,
	result_4,
	result_5,
	result_6,
	result_7,
	result_8,
	result_9,
	result_10,
	result_11,
	result_12,
	result_13,
	result_14,
	result_15,
	devclrn,
	devpor,
	devoe,
	tx_out,
	tx_outclock);
input 	pll;
input 	pll1;
input 	pll2;
input 	rx_outclock;
input 	result_0;
input 	result_1;
input 	result_2;
input 	result_3;
input 	result_4;
input 	result_5;
input 	result_6;
input 	result_7;
input 	result_8;
input 	result_9;
input 	result_10;
input 	result_11;
input 	result_12;
input 	result_13;
input 	result_14;
input 	result_15;
input 	devclrn;
input 	devpor;
input 	devoe;
output 	[1:0] tx_out;
output 	tx_outclock;

supply0 gnd;
supply1 vcc;

wire \altlvds_tx_component|txreg[8] ;
wire \altlvds_tx_component|txreg[9] ;
wire \altlvds_tx_component|txreg[10] ;
wire \altlvds_tx_component|txreg[11] ;
wire \altlvds_tx_component|txreg[12] ;
wire \altlvds_tx_component|txreg[13] ;
wire \altlvds_tx_component|txreg[14] ;
wire \altlvds_tx_component|txreg[15] ;
wire \altlvds_tx_component|txreg[0] ;
wire \altlvds_tx_component|txreg[1] ;
wire \altlvds_tx_component|txreg[2] ;
wire \altlvds_tx_component|txreg[3] ;
wire \altlvds_tx_component|txreg[4] ;
wire \altlvds_tx_component|txreg[5] ;
wire \altlvds_tx_component|txreg[6] ;
wire \altlvds_tx_component|txreg[7] ;


// atom is at SERDESTX_X0_Y61_N5
stratix_lvds_transmitter \altlvds_tx_component|tx[1] (
	.clk0(pll1),
	.enable0(pll),
	.datain({gnd,gnd,\altlvds_tx_component|txreg[15] ,\altlvds_tx_component|txreg[14] ,\altlvds_tx_component|txreg[13] ,\altlvds_tx_component|txreg[12] ,\altlvds_tx_component|txreg[11] ,\altlvds_tx_component|txreg[10] ,\altlvds_tx_component|txreg[9] ,
\altlvds_tx_component|txreg[8] }),
	.devclrn(devclrn),
	.devpor(devpor),
	.dataout(tx_out[1]));
// synopsys translate_off
defparam \altlvds_tx_component|tx[1] .channel_width = 8;
defparam \altlvds_tx_component|tx[1] .bypass_serializer = "false";
defparam \altlvds_tx_component|tx[1] .invert_clock = "false";
defparam \altlvds_tx_component|tx[1] .use_falling_clock_edge = "false";
// synopsys translate_on

// atom is at SERDESTX_X0_Y60_N5
stratix_lvds_transmitter \altlvds_tx_component|tx[0] (
	.clk0(pll1),
	.enable0(pll),
	.datain({gnd,gnd,\altlvds_tx_component|txreg[7] ,\altlvds_tx_component|txreg[6] ,\altlvds_tx_component|txreg[5] ,\altlvds_tx_component|txreg[4] ,\altlvds_tx_component|txreg[3] ,\altlvds_tx_component|txreg[2] ,\altlvds_tx_component|txreg[1] ,\altlvds_tx_component|txreg[0] }),
	.devclrn(devclrn),
	.devpor(devpor),
	.dataout(tx_out[0]));
// synopsys translate_off
defparam \altlvds_tx_component|tx[0] .channel_width = 8;
defparam \altlvds_tx_component|tx[0] .bypass_serializer = "false";
defparam \altlvds_tx_component|tx[0] .invert_clock = "false";
defparam \altlvds_tx_component|tx[0] .use_falling_clock_edge = "false";
// synopsys translate_on

// atom is at SERDESTX_X0_Y59_N5
stratix_lvds_transmitter \altlvds_tx_component|outclock_tx (
	.clk0(pll2),
	.enable0(pll),
	.datain({gnd,gnd,vcc,vcc,gnd,gnd,gnd,gnd,vcc,vcc}),
	.devclrn(devclrn),
	.devpor(devpor),
	.dataout(tx_outclock));
// synopsys translate_off
defparam \altlvds_tx_component|outclock_tx .channel_width = 8;
defparam \altlvds_tx_component|outclock_tx .bypass_serializer = "false";
defparam \altlvds_tx_component|outclock_tx .invert_clock = "false";
defparam \altlvds_tx_component|outclock_tx .use_falling_clock_edge = "false";
// synopsys translate_on

// atom is at LC_X3_Y61_N2
stratix_lcell \altlvds_tx_component|txreg[8]~I (
// Equation(s):
// \altlvds_tx_component|txreg[8]  = DFFEA(result, GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(result_8),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\altlvds_tx_component|txreg[8] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_tx_component|txreg[8]~I .operation_mode = "normal";
defparam \altlvds_tx_component|txreg[8]~I .synch_mode = "off";
defparam \altlvds_tx_component|txreg[8]~I .register_cascade_mode = "off";
defparam \altlvds_tx_component|txreg[8]~I .sum_lutc_input = "datac";
defparam \altlvds_tx_component|txreg[8]~I .lut_mask = "FF00";
defparam \altlvds_tx_component|txreg[8]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X3_Y61_N8
stratix_lcell \altlvds_tx_component|txreg[9]~I (
// Equation(s):
// \altlvds_tx_component|txreg[9]  = DFFEA(result, GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(result_9),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\altlvds_tx_component|txreg[9] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_tx_component|txreg[9]~I .operation_mode = "normal";
defparam \altlvds_tx_component|txreg[9]~I .synch_mode = "off";
defparam \altlvds_tx_component|txreg[9]~I .register_cascade_mode = "off";
defparam \altlvds_tx_component|txreg[9]~I .sum_lutc_input = "datac";
defparam \altlvds_tx_component|txreg[9]~I .lut_mask = "FF00";
defparam \altlvds_tx_component|txreg[9]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X3_Y61_N9
stratix_lcell \altlvds_tx_component|txreg[10]~I (
// Equation(s):
// \altlvds_tx_component|txreg[10]  = DFFEA(result, GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(result_10),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\altlvds_tx_component|txreg[10] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_tx_component|txreg[10]~I .operation_mode = "normal";
defparam \altlvds_tx_component|txreg[10]~I .synch_mode = "off";
defparam \altlvds_tx_component|txreg[10]~I .register_cascade_mode = "off";
defparam \altlvds_tx_component|txreg[10]~I .sum_lutc_input = "datac";
defparam \altlvds_tx_component|txreg[10]~I .lut_mask = "FF00";
defparam \altlvds_tx_component|txreg[10]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X3_Y61_N3
stratix_lcell \altlvds_tx_component|txreg[11]~I (
// Equation(s):
// \altlvds_tx_component|txreg[11]  = DFFEA(result, GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(result_11),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\altlvds_tx_component|txreg[11] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_tx_component|txreg[11]~I .operation_mode = "normal";
defparam \altlvds_tx_component|txreg[11]~I .synch_mode = "off";
defparam \altlvds_tx_component|txreg[11]~I .register_cascade_mode = "off";
defparam \altlvds_tx_component|txreg[11]~I .sum_lutc_input = "datac";
defparam \altlvds_tx_component|txreg[11]~I .lut_mask = "FF00";
defparam \altlvds_tx_component|txreg[11]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X3_Y61_N5
stratix_lcell \altlvds_tx_component|txreg[12]~I (
// Equation(s):
// \altlvds_tx_component|txreg[12]  = DFFEA(result, GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(result_12),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\altlvds_tx_component|txreg[12] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_tx_component|txreg[12]~I .operation_mode = "normal";
defparam \altlvds_tx_component|txreg[12]~I .synch_mode = "off";
defparam \altlvds_tx_component|txreg[12]~I .register_cascade_mode = "off";
defparam \altlvds_tx_component|txreg[12]~I .sum_lutc_input = "datac";
defparam \altlvds_tx_component|txreg[12]~I .lut_mask = "FF00";
defparam \altlvds_tx_component|txreg[12]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X3_Y61_N4
stratix_lcell \altlvds_tx_component|txreg[13]~I (
// Equation(s):
// \altlvds_tx_component|txreg[13]  = DFFEA(result, GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(result_13),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\altlvds_tx_component|txreg[13] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_tx_component|txreg[13]~I .operation_mode = "normal";
defparam \altlvds_tx_component|txreg[13]~I .synch_mode = "off";
defparam \altlvds_tx_component|txreg[13]~I .register_cascade_mode = "off";
defparam \altlvds_tx_component|txreg[13]~I .sum_lutc_input = "datac";
defparam \altlvds_tx_component|txreg[13]~I .lut_mask = "FF00";
defparam \altlvds_tx_component|txreg[13]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X3_Y61_N7
stratix_lcell \altlvds_tx_component|txreg[14]~I (
// Equation(s):
// \altlvds_tx_component|txreg[14]  = DFFEA(result, GLOBAL(rx_outclock), VCC, , , )