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📄 diff_io_top.vo

📁 这个verilog代码是一个输入输出经典的例子。大家一起参考。
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// Equation(s):
// rx_out = DFFEA(\altlvds_rx_component|rx[1]~DATAOUT2 , GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\altlvds_rx_component|rx[1]~DATAOUT2 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(rx_out[10]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_rx_component|rxreg[10]~I .operation_mode = "normal";
defparam \altlvds_rx_component|rxreg[10]~I .synch_mode = "off";
defparam \altlvds_rx_component|rxreg[10]~I .register_cascade_mode = "off";
defparam \altlvds_rx_component|rxreg[10]~I .sum_lutc_input = "datac";
defparam \altlvds_rx_component|rxreg[10]~I .lut_mask = "FF00";
defparam \altlvds_rx_component|rxreg[10]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X1_Y48_N0
stratix_lcell \altlvds_rx_component|rxreg[9]~I (
// Equation(s):
// rx_out = DFFEA(\altlvds_rx_component|rx[1]~DATAOUT1 , GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\altlvds_rx_component|rx[1]~DATAOUT1 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(rx_out[9]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_rx_component|rxreg[9]~I .operation_mode = "normal";
defparam \altlvds_rx_component|rxreg[9]~I .synch_mode = "off";
defparam \altlvds_rx_component|rxreg[9]~I .register_cascade_mode = "off";
defparam \altlvds_rx_component|rxreg[9]~I .sum_lutc_input = "datac";
defparam \altlvds_rx_component|rxreg[9]~I .lut_mask = "FF00";
defparam \altlvds_rx_component|rxreg[9]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X1_Y48_N8
stratix_lcell \altlvds_rx_component|rxreg[8]~I (
// Equation(s):
// rx_out = DFFEA(\altlvds_rx_component|rx[1] , GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\altlvds_rx_component|rx[1] ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(rx_out[8]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_rx_component|rxreg[8]~I .operation_mode = "normal";
defparam \altlvds_rx_component|rxreg[8]~I .synch_mode = "off";
defparam \altlvds_rx_component|rxreg[8]~I .register_cascade_mode = "off";
defparam \altlvds_rx_component|rxreg[8]~I .sum_lutc_input = "datac";
defparam \altlvds_rx_component|rxreg[8]~I .lut_mask = "FF00";
defparam \altlvds_rx_component|rxreg[8]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X1_Y49_N3
stratix_lcell \altlvds_rx_component|rxreg[7]~I (
// Equation(s):
// rx_out = DFFEA(\altlvds_rx_component|rx[0]~DATAOUT7 , GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\altlvds_rx_component|rx[0]~DATAOUT7 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(rx_out[7]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_rx_component|rxreg[7]~I .operation_mode = "normal";
defparam \altlvds_rx_component|rxreg[7]~I .synch_mode = "off";
defparam \altlvds_rx_component|rxreg[7]~I .register_cascade_mode = "off";
defparam \altlvds_rx_component|rxreg[7]~I .sum_lutc_input = "datac";
defparam \altlvds_rx_component|rxreg[7]~I .lut_mask = "FF00";
defparam \altlvds_rx_component|rxreg[7]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X1_Y49_N6
stratix_lcell \altlvds_rx_component|rxreg[6]~I (
// Equation(s):
// rx_out = DFFEA(\altlvds_rx_component|rx[0]~DATAOUT6 , GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\altlvds_rx_component|rx[0]~DATAOUT6 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(rx_out[6]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_rx_component|rxreg[6]~I .operation_mode = "normal";
defparam \altlvds_rx_component|rxreg[6]~I .synch_mode = "off";
defparam \altlvds_rx_component|rxreg[6]~I .register_cascade_mode = "off";
defparam \altlvds_rx_component|rxreg[6]~I .sum_lutc_input = "datac";
defparam \altlvds_rx_component|rxreg[6]~I .lut_mask = "FF00";
defparam \altlvds_rx_component|rxreg[6]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X1_Y49_N1
stratix_lcell \altlvds_rx_component|rxreg[5]~I (
// Equation(s):
// rx_out = DFFEA(\altlvds_rx_component|rx[0]~DATAOUT5 , GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\altlvds_rx_component|rx[0]~DATAOUT5 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(rx_out[5]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_rx_component|rxreg[5]~I .operation_mode = "normal";
defparam \altlvds_rx_component|rxreg[5]~I .synch_mode = "off";
defparam \altlvds_rx_component|rxreg[5]~I .register_cascade_mode = "off";
defparam \altlvds_rx_component|rxreg[5]~I .sum_lutc_input = "datac";
defparam \altlvds_rx_component|rxreg[5]~I .lut_mask = "FF00";
defparam \altlvds_rx_component|rxreg[5]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X1_Y49_N4
stratix_lcell \altlvds_rx_component|rxreg[4]~I (
// Equation(s):
// rx_out = DFFEA(\altlvds_rx_component|rx[0]~DATAOUT4 , GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\altlvds_rx_component|rx[0]~DATAOUT4 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(rx_out[4]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_rx_component|rxreg[4]~I .operation_mode = "normal";
defparam \altlvds_rx_component|rxreg[4]~I .synch_mode = "off";
defparam \altlvds_rx_component|rxreg[4]~I .register_cascade_mode = "off";
defparam \altlvds_rx_component|rxreg[4]~I .sum_lutc_input = "datac";
defparam \altlvds_rx_component|rxreg[4]~I .lut_mask = "FF00";
defparam \altlvds_rx_component|rxreg[4]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X1_Y49_N5
stratix_lcell \altlvds_rx_component|rxreg[3]~I (
// Equation(s):
// rx_out = DFFEA(\altlvds_rx_component|rx[0]~DATAOUT3 , GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\altlvds_rx_component|rx[0]~DATAOUT3 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(rx_out[3]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_rx_component|rxreg[3]~I .operation_mode = "normal";
defparam \altlvds_rx_component|rxreg[3]~I .synch_mode = "off";
defparam \altlvds_rx_component|rxreg[3]~I .register_cascade_mode = "off";
defparam \altlvds_rx_component|rxreg[3]~I .sum_lutc_input = "datac";
defparam \altlvds_rx_component|rxreg[3]~I .lut_mask = "FF00";
defparam \altlvds_rx_component|rxreg[3]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X1_Y49_N7
stratix_lcell \altlvds_rx_component|rxreg[2]~I (
// Equation(s):
// rx_out = DFFEA(\altlvds_rx_component|rx[0]~DATAOUT2 , GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\altlvds_rx_component|rx[0]~DATAOUT2 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(rx_out[2]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_rx_component|rxreg[2]~I .operation_mode = "normal";
defparam \altlvds_rx_component|rxreg[2]~I .synch_mode = "off";
defparam \altlvds_rx_component|rxreg[2]~I .register_cascade_mode = "off";
defparam \altlvds_rx_component|rxreg[2]~I .sum_lutc_input = "datac";
defparam \altlvds_rx_component|rxreg[2]~I .lut_mask = "FF00";
defparam \altlvds_rx_component|rxreg[2]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X1_Y49_N9
stratix_lcell \altlvds_rx_component|rxreg[1]~I (
// Equation(s):
// rx_out = DFFEA(\altlvds_rx_component|rx[0]~DATAOUT1 , GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\altlvds_rx_component|rx[0]~DATAOUT1 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(rx_out[1]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_rx_component|rxreg[1]~I .operation_mode = "normal";
defparam \altlvds_rx_component|rxreg[1]~I .synch_mode = "off";
defparam \altlvds_rx_component|rxreg[1]~I .register_cascade_mode = "off";
defparam \altlvds_rx_component|rxreg[1]~I .sum_lutc_input = "datac";
defparam \altlvds_rx_component|rxreg[1]~I .lut_mask = "FF00";
defparam \altlvds_rx_component|rxreg[1]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X1_Y49_N2
stratix_lcell \altlvds_rx_component|rxreg[0]~I (
// Equation(s):
// rx_out = DFFEA(\altlvds_rx_component|rx[0] , GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\altlvds_rx_component|rx[0] ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(rx_out[0]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_rx_component|rxreg[0]~I .operation_mode = "normal";
defparam \altlvds_rx_component|rxreg[0]~I .synch_mode = "off";
defparam \altlvds_rx_component|rxreg[0]~I .register_cascade_mode = "off";
defparam \altlvds_rx_component|rxreg[0]~I .sum_lutc_input = "datac";
defparam \altlvds_rx_component|rxreg[0]~I .lut_mask = "FF00";
defparam \altlvds_rx_component|rxreg[0]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X1_Y41_N2
stratix_lcell \altlvds_rx_component|pll~0_I (
// Equation(s):
// rx_locked = LCELL(!\altlvds_rx_component|pll~LOCKED )

	.clk(),
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