diff_io_top.vo

这个verilog代码是一个输入输出经典的例子。大家一起参考。

defparam \tx_out[0]~I .output_sync_reset = "none";
defparam \tx_out[0]~I .oe_sync_reset = "none";
defparam \tx_out[0]~I .input_power_up = "low";
defparam \tx_out[0]~I .output_power_up = "low";
defparam \tx_out[0]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_P32
stratix_io \tx_outclock~I (
	.datain(\lvds_tx_inst|altlvds_tx_component|tx_outclock ),
	.ddiodatain(),
	.oe(vcc),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(tx_outclock));
// synopsys translate_off
defparam \tx_outclock~I .operation_mode = "output";
defparam \tx_outclock~I .ddio_mode = "none";
defparam \tx_outclock~I .output_register_mode = "none";
defparam \tx_outclock~I .oe_register_mode = "none";
defparam \tx_outclock~I .input_async_reset = "none";
defparam \tx_outclock~I .output_async_reset = "none";
defparam \tx_outclock~I .oe_async_reset = "none";
defparam \tx_outclock~I .input_sync_reset = "none";
defparam \tx_outclock~I .output_sync_reset = "none";
defparam \tx_outclock~I .oe_sync_reset = "none";
defparam \tx_outclock~I .input_power_up = "low";
defparam \tx_outclock~I .output_power_up = "low";
defparam \tx_outclock~I .oe_power_up = "low";
// synopsys translate_on

endmodule

module 	lvds_rx (
	rx_data_align,
	rx_in,
	rx_inclock,
	devclrn,
	devpor,
	devoe,
	pll,
	pll1,
	pll2,
	rx_outclock,
	rx_out,
	rx_locked);
input 	rx_data_align;
input 	[1:0] rx_in;
input 	rx_inclock;
input 	devclrn;
input 	devpor;
input 	devoe;
output 	pll;
output 	pll1;
output 	pll2;
output 	rx_outclock;
output 	[15:0] rx_out;
output 	rx_locked;

supply0 gnd;
supply1 vcc;

wire \altlvds_rx_component|rx[1]~LOCKED ;
wire \altlvds_rx_component|rx[0]~LOCKED ;
wire \altlvds_rx_component|pll~ACTIVECLOCK ;
wire \altlvds_rx_component|pll~GLOCKED ;
wire \altlvds_rx_component|pll~SCANDATAOUT ;
wire \altlvds_rx_component|pll~CLK3 ;
wire \altlvds_rx_component|pll~CLK4 ;
wire \altlvds_rx_component|pll~CLK5 ;
wire \altlvds_rx_component|pll~EXTCLK0 ;
wire \altlvds_rx_component|pll~EXTCLK1 ;
wire \altlvds_rx_component|pll~EXTCLK2 ;
wire \altlvds_rx_component|pll~EXTCLK3 ;
wire \altlvds_rx_component|pll~CLKBAD0 ;
wire \altlvds_rx_component|pll~CLKBAD1 ;
wire \altlvds_rx_component|pll~LOCKED ;
wire \altlvds_rx_component|pll~ENAOUT0 ;
wire \altlvds_rx_component|rx[1]~DATAOUT7 ;
wire \altlvds_rx_component|rx[1]~DATAOUT6 ;
wire \altlvds_rx_component|rx[1]~DATAOUT5 ;
wire \altlvds_rx_component|rx[1]~DATAOUT4 ;
wire \altlvds_rx_component|rx[1]~DATAOUT3 ;
wire \altlvds_rx_component|rx[1]~DATAOUT2 ;
wire \altlvds_rx_component|rx[1]~DATAOUT1 ;
wire \altlvds_rx_component|rx[1] ;
wire \altlvds_rx_component|rx[0]~DATAOUT7 ;
wire \altlvds_rx_component|rx[0]~DATAOUT6 ;
wire \altlvds_rx_component|rx[0]~DATAOUT5 ;
wire \altlvds_rx_component|rx[0]~DATAOUT4 ;
wire \altlvds_rx_component|rx[0]~DATAOUT3 ;
wire \altlvds_rx_component|rx[0]~DATAOUT2 ;
wire \altlvds_rx_component|rx[0]~DATAOUT1 ;
wire \altlvds_rx_component|rx[0] ;

wire [9:0] \ww_altlvds_rx_component|rx[1]~I_dataout ;
wire [9:0] \ww_altlvds_rx_component|rx[0]~I_dataout ;
wire [5:0] \ww_altlvds_rx_component|pll~I_clk ;

assign \altlvds_rx_component|rx[1]  = \ww_altlvds_rx_component|rx[1]~I_dataout [0];
assign \altlvds_rx_component|rx[1]~DATAOUT1  = \ww_altlvds_rx_component|rx[1]~I_dataout [1];
assign \altlvds_rx_component|rx[1]~DATAOUT2  = \ww_altlvds_rx_component|rx[1]~I_dataout [2];
assign \altlvds_rx_component|rx[1]~DATAOUT3  = \ww_altlvds_rx_component|rx[1]~I_dataout [3];
assign \altlvds_rx_component|rx[1]~DATAOUT4  = \ww_altlvds_rx_component|rx[1]~I_dataout [4];
assign \altlvds_rx_component|rx[1]~DATAOUT5  = \ww_altlvds_rx_component|rx[1]~I_dataout [5];
assign \altlvds_rx_component|rx[1]~DATAOUT6  = \ww_altlvds_rx_component|rx[1]~I_dataout [6];
assign \altlvds_rx_component|rx[1]~DATAOUT7  = \ww_altlvds_rx_component|rx[1]~I_dataout [7];

assign \altlvds_rx_component|rx[0]  = \ww_altlvds_rx_component|rx[0]~I_dataout [0];
assign \altlvds_rx_component|rx[0]~DATAOUT1  = \ww_altlvds_rx_component|rx[0]~I_dataout [1];
assign \altlvds_rx_component|rx[0]~DATAOUT2  = \ww_altlvds_rx_component|rx[0]~I_dataout [2];
assign \altlvds_rx_component|rx[0]~DATAOUT3  = \ww_altlvds_rx_component|rx[0]~I_dataout [3];
assign \altlvds_rx_component|rx[0]~DATAOUT4  = \ww_altlvds_rx_component|rx[0]~I_dataout [4];
assign \altlvds_rx_component|rx[0]~DATAOUT5  = \ww_altlvds_rx_component|rx[0]~I_dataout [5];
assign \altlvds_rx_component|rx[0]~DATAOUT6  = \ww_altlvds_rx_component|rx[0]~I_dataout [6];
assign \altlvds_rx_component|rx[0]~DATAOUT7  = \ww_altlvds_rx_component|rx[0]~I_dataout [7];

assign pll1 = \ww_altlvds_rx_component|pll~I_clk [0];
assign pll2 = \ww_altlvds_rx_component|pll~I_clk [1];
assign rx_outclock = \ww_altlvds_rx_component|pll~I_clk [2];

// atom is at PLL_1
stratix_pll \altlvds_rx_component|pll~I (
	.fbin(vcc),
	.ena(vcc),
	.clkswitch(gnd),
	.areset(gnd),
	.pfdena(vcc),
	.scanclk(),
	.scanaclr(gnd),
	.scandata(gnd),
	.comparator(rx_data_align),
	.inclk({gnd,rx_inclock}),
	.clkena({vcc,vcc,vcc,vcc,vcc,vcc}),
	.extclkena(),
	.activeclock(),
	.clkloss(),
	.locked(\altlvds_rx_component|pll~LOCKED ),
	.scandataout(),
	.enable0(\altlvds_rx_component|pll~ENAOUT0 ),
	.enable1(pll),
	.clk(\ww_altlvds_rx_component|pll~I_clk ),
	.extclk(),
	.clkbad());
// synopsys translate_off
defparam \altlvds_rx_component|pll~I .operation_mode = "normal";
defparam \altlvds_rx_component|pll~I .pll_type = "fast";
defparam \altlvds_rx_component|pll~I .qualify_conf_done = "off";
defparam \altlvds_rx_component|pll~I .lock_high = 5;
defparam \altlvds_rx_component|pll~I .lock_low = 5;
defparam \altlvds_rx_component|pll~I .valid_lock_multiplier = 1;
defparam \altlvds_rx_component|pll~I .invalid_lock_multiplier = 5;
defparam \altlvds_rx_component|pll~I .compensate_clock = "lvdsclk";
defparam \altlvds_rx_component|pll~I .inclk0_input_frequency = 9523;
defparam \altlvds_rx_component|pll~I .inclk1_input_frequency = 9523;
defparam \altlvds_rx_component|pll~I .pfd_min = 2000;
defparam \altlvds_rx_component|pll~I .pfd_max = 66666;
defparam \altlvds_rx_component|pll~I .vco_min = 1000;
defparam \altlvds_rx_component|pll~I .vco_max = 3334;
defparam \altlvds_rx_component|pll~I .vco_center = 1250;
defparam \altlvds_rx_component|pll~I .pll_compensation_delay = 1269;
defparam \altlvds_rx_component|pll~I .source_is_pll = "off";
defparam \altlvds_rx_component|pll~I .common_rx_tx = "on";
defparam \altlvds_rx_component|pll~I .rx_outclock_resource = "auto";
defparam \altlvds_rx_component|pll~I .primary_clock = "inclk0";
defparam \altlvds_rx_component|pll~I .switch_over_on_lossclk = "off";
defparam \altlvds_rx_component|pll~I .switch_over_on_gated_lock = "off";
defparam \altlvds_rx_component|pll~I .enable_switch_over_counter = "off";
defparam \altlvds_rx_component|pll~I .gate_lock_signal = "no";
defparam \altlvds_rx_component|pll~I .gate_lock_counter = 0;
defparam \altlvds_rx_component|pll~I .switch_over_counter = 1;
defparam \altlvds_rx_component|pll~I .m = 8;
defparam \altlvds_rx_component|pll~I .n = 1;
defparam \altlvds_rx_component|pll~I .clk0_counter = "l0";
defparam \altlvds_rx_component|pll~I .clk1_counter = "l1";
defparam \altlvds_rx_component|pll~I .clk2_counter = "g0";
defparam \altlvds_rx_component|pll~I .enable0_counter = "l0";
defparam \altlvds_rx_component|pll~I .enable1_counter = "l1";
defparam \altlvds_rx_component|pll~I .l0_mode = "bypass";
defparam \altlvds_rx_component|pll~I .l1_mode = "bypass";
defparam \altlvds_rx_component|pll~I .g0_mode = "even";
defparam \altlvds_rx_component|pll~I .l0_high = 4;
defparam \altlvds_rx_component|pll~I .l1_high = 4;
defparam \altlvds_rx_component|pll~I .g0_high = 4;
defparam \altlvds_rx_component|pll~I .l0_low = 4;
defparam \altlvds_rx_component|pll~I .l1_low = 4;
defparam \altlvds_rx_component|pll~I .g0_low = 4;
defparam \altlvds_rx_component|pll~I .m_initial = 1;
defparam \altlvds_rx_component|pll~I .g0_initial = 1;
defparam \altlvds_rx_component|pll~I .m_ph = 0;
defparam \altlvds_rx_component|pll~I .l0_ph = 0;
defparam \altlvds_rx_component|pll~I .l1_ph = 0;
defparam \altlvds_rx_component|pll~I .g0_ph = 0;
defparam \altlvds_rx_component|pll~I .clk0_multiply_by = 8;
defparam \altlvds_rx_component|pll~I .clk1_multiply_by = 8;
defparam \altlvds_rx_component|pll~I .clk2_multiply_by = 1;
defparam \altlvds_rx_component|pll~I .clk0_divide_by = 1;
defparam \altlvds_rx_component|pll~I .clk1_divide_by = 1;
defparam \altlvds_rx_component|pll~I .clk2_divide_by = 1;
defparam \altlvds_rx_component|pll~I .clk0_phase_shift = "0";
defparam \altlvds_rx_component|pll~I .clk1_phase_shift = "0";
defparam \altlvds_rx_component|pll~I .clk2_phase_shift = "0";
defparam \altlvds_rx_component|pll~I .clk0_duty_cycle = 50;
defparam \altlvds_rx_component|pll~I .clk1_duty_cycle = 50;
defparam \altlvds_rx_component|pll~I .clk2_duty_cycle = 50;
defparam \altlvds_rx_component|pll~I .simulation_type = "timing";
// synopsys translate_on

// atom is at LC_X1_Y48_N9
stratix_lcell \altlvds_rx_component|rxreg[15]~I (
// Equation(s):
// rx_out = DFFEA(\altlvds_rx_component|rx[1]~DATAOUT7 , GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\altlvds_rx_component|rx[1]~DATAOUT7 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(rx_out[15]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_rx_component|rxreg[15]~I .operation_mode = "normal";
defparam \altlvds_rx_component|rxreg[15]~I .synch_mode = "off";
defparam \altlvds_rx_component|rxreg[15]~I .register_cascade_mode = "off";
defparam \altlvds_rx_component|rxreg[15]~I .sum_lutc_input = "datac";
defparam \altlvds_rx_component|rxreg[15]~I .lut_mask = "FF00";
defparam \altlvds_rx_component|rxreg[15]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X1_Y48_N5
stratix_lcell \altlvds_rx_component|rxreg[14]~I (
// Equation(s):
// rx_out = DFFEA(\altlvds_rx_component|rx[1]~DATAOUT6 , GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\altlvds_rx_component|rx[1]~DATAOUT6 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(rx_out[14]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_rx_component|rxreg[14]~I .operation_mode = "normal";
defparam \altlvds_rx_component|rxreg[14]~I .synch_mode = "off";
defparam \altlvds_rx_component|rxreg[14]~I .register_cascade_mode = "off";
defparam \altlvds_rx_component|rxreg[14]~I .sum_lutc_input = "datac";
defparam \altlvds_rx_component|rxreg[14]~I .lut_mask = "FF00";
defparam \altlvds_rx_component|rxreg[14]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X1_Y48_N7
stratix_lcell \altlvds_rx_component|rxreg[13]~I (
// Equation(s):
// rx_out = DFFEA(\altlvds_rx_component|rx[1]~DATAOUT5 , GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\altlvds_rx_component|rx[1]~DATAOUT5 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(rx_out[13]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_rx_component|rxreg[13]~I .operation_mode = "normal";
defparam \altlvds_rx_component|rxreg[13]~I .synch_mode = "off";
defparam \altlvds_rx_component|rxreg[13]~I .register_cascade_mode = "off";
defparam \altlvds_rx_component|rxreg[13]~I .sum_lutc_input = "datac";
defparam \altlvds_rx_component|rxreg[13]~I .lut_mask = "FF00";
defparam \altlvds_rx_component|rxreg[13]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X1_Y48_N4
stratix_lcell \altlvds_rx_component|rxreg[12]~I (
// Equation(s):
// rx_out = DFFEA(\altlvds_rx_component|rx[1]~DATAOUT4 , GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\altlvds_rx_component|rx[1]~DATAOUT4 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(rx_out[12]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_rx_component|rxreg[12]~I .operation_mode = "normal";
defparam \altlvds_rx_component|rxreg[12]~I .synch_mode = "off";
defparam \altlvds_rx_component|rxreg[12]~I .register_cascade_mode = "off";
defparam \altlvds_rx_component|rxreg[12]~I .sum_lutc_input = "datac";
defparam \altlvds_rx_component|rxreg[12]~I .lut_mask = "FF00";
defparam \altlvds_rx_component|rxreg[12]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X1_Y48_N6
stratix_lcell \altlvds_rx_component|rxreg[11]~I (
// Equation(s):
// rx_out = DFFEA(\altlvds_rx_component|rx[1]~DATAOUT3 , GLOBAL(rx_outclock), VCC, , , )

	.clk(rx_outclock),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\altlvds_rx_component|rx[1]~DATAOUT3 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(rx_out[11]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \altlvds_rx_component|rxreg[11]~I .operation_mode = "normal";
defparam \altlvds_rx_component|rxreg[11]~I .synch_mode = "off";
defparam \altlvds_rx_component|rxreg[11]~I .register_cascade_mode = "off";
defparam \altlvds_rx_component|rxreg[11]~I .sum_lutc_input = "datac";
defparam \altlvds_rx_component|rxreg[11]~I .lut_mask = "FF00";
defparam \altlvds_rx_component|rxreg[11]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X1_Y48_N1
stratix_lcell \altlvds_rx_component|rxreg[10]~I (