diff_io_top.vo

这个verilog代码是一个输入输出经典的例子。大家一起参考。

// Copyright (C) 1991-2002 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 2.2 Build 147 12/02/2002 SJ Full Version"

// DATE "01/23/2003 15:19:15"

//
// Device: Altera EP1S60F1508C6 Package FBGA1508
// 

// 
// This Verilog file should be used for MODELSIM (VERILOG HDL OUTPUT FROM QUARTUS II) only
// 

`timescale 1 ps/ 1 ps

module 	Diff_io_top (
	rx_data_align,
	rx_in,
	rx_inclock,
	rx_locked,
	tx_out,
	tx_outclock);
input 	rx_data_align;
input 	[1:0] rx_in;
input 	rx_inclock;
output 	rx_locked;
output 	[1:0] tx_out;
output 	tx_outclock;

supply0 gnd;
supply1 vcc;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("Diff_io_top_v.sdo");
// synopsys translate_on

wire \lvds_rx_inst|altlvds_rx_component|pll~ENAOUT1 ;
wire \lvds_rx_inst|altlvds_rx_component|pll ;
wire \lvds_rx_inst|altlvds_rx_component|pll~CLK1 ;
wire \lvds_rx_inst|altlvds_rx_component|rx_outclock ;
wire \lvds_rx_inst|altlvds_rx_component|rxreg[15] ;
wire \lvds_rx_inst|altlvds_rx_component|rxreg[14] ;
wire \lvds_rx_inst|altlvds_rx_component|rxreg[13] ;
wire \lvds_rx_inst|altlvds_rx_component|rxreg[12] ;
wire \lvds_rx_inst|altlvds_rx_component|rxreg[11] ;
wire \lvds_rx_inst|altlvds_rx_component|rxreg[10] ;
wire \lvds_rx_inst|altlvds_rx_component|rxreg[9] ;
wire \lvds_rx_inst|altlvds_rx_component|rxreg[8] ;
wire \lvds_rx_inst|altlvds_rx_component|rxreg[7] ;
wire \lvds_rx_inst|altlvds_rx_component|rxreg[6] ;
wire \lvds_rx_inst|altlvds_rx_component|rxreg[5] ;
wire \lvds_rx_inst|altlvds_rx_component|rxreg[4] ;
wire \lvds_rx_inst|altlvds_rx_component|rxreg[3] ;
wire \lvds_rx_inst|altlvds_rx_component|rxreg[2] ;
wire \lvds_rx_inst|altlvds_rx_component|rxreg[1] ;
wire \lvds_rx_inst|altlvds_rx_component|rxreg[0] ;
wire \lvds_rx_inst|altlvds_rx_component|pll~0 ;
wire \mult_inst|lpm_mult_component|auto_generated|result[0] ;
wire \mult_inst|lpm_mult_component|auto_generated|result[1] ;
wire \mult_inst|lpm_mult_component|auto_generated|result[2] ;
wire \mult_inst|lpm_mult_component|auto_generated|result[3] ;
wire \mult_inst|lpm_mult_component|auto_generated|result[4] ;
wire \mult_inst|lpm_mult_component|auto_generated|result[5] ;
wire \mult_inst|lpm_mult_component|auto_generated|result[6] ;
wire \mult_inst|lpm_mult_component|auto_generated|result[7] ;
wire \mult_inst|lpm_mult_component|auto_generated|result[8] ;
wire \mult_inst|lpm_mult_component|auto_generated|result[9] ;
wire \mult_inst|lpm_mult_component|auto_generated|result[10] ;
wire \mult_inst|lpm_mult_component|auto_generated|result[11] ;
wire \mult_inst|lpm_mult_component|auto_generated|result[12] ;
wire \mult_inst|lpm_mult_component|auto_generated|result[13] ;
wire \mult_inst|lpm_mult_component|auto_generated|result[14] ;
wire \mult_inst|lpm_mult_component|auto_generated|result[15] ;
wire \lvds_tx_inst|altlvds_tx_component|tx_out[1] ;
wire \lvds_tx_inst|altlvds_tx_component|tx_out[0] ;
wire \lvds_tx_inst|altlvds_tx_component|tx_outclock ;
wire \rx_data_align~padio ;
wire \rx_data_align~combout ;
wire \rx_in[0]~padio ;
wire \rx_in[0]~combout ;
wire \rx_in[1]~padio ;
wire \rx_in[1]~combout ;
wire \rx_inclock~padio ;
wire \rx_inclock~combout ;
wire \rx_locked~padio ;
wire \tx_out[1]~padio ;
wire \tx_out[0]~padio ;
wire \tx_outclock~padio ;

lvds_rx lvds_rx_inst(
	.rx_data_align(\rx_data_align~combout ),
	.rx_in({\rx_in[1]~combout ,\rx_in[0]~combout }),
	.rx_inclock(\rx_inclock~combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.pll(\lvds_rx_inst|altlvds_rx_component|pll~ENAOUT1 ),
	.pll1(\lvds_rx_inst|altlvds_rx_component|pll ),
	.pll2(\lvds_rx_inst|altlvds_rx_component|pll~CLK1 ),
	.rx_outclock(\lvds_rx_inst|altlvds_rx_component|rx_outclock ),
	.rx_out({\lvds_rx_inst|altlvds_rx_component|rxreg[15] ,\lvds_rx_inst|altlvds_rx_component|rxreg[14] ,\lvds_rx_inst|altlvds_rx_component|rxreg[13] ,\lvds_rx_inst|altlvds_rx_component|rxreg[12] ,\lvds_rx_inst|altlvds_rx_component|rxreg[11] ,
\lvds_rx_inst|altlvds_rx_component|rxreg[10] ,\lvds_rx_inst|altlvds_rx_component|rxreg[9] ,\lvds_rx_inst|altlvds_rx_component|rxreg[8] ,\lvds_rx_inst|altlvds_rx_component|rxreg[7] ,\lvds_rx_inst|altlvds_rx_component|rxreg[6] ,
\lvds_rx_inst|altlvds_rx_component|rxreg[5] ,\lvds_rx_inst|altlvds_rx_component|rxreg[4] ,\lvds_rx_inst|altlvds_rx_component|rxreg[3] ,\lvds_rx_inst|altlvds_rx_component|rxreg[2] ,\lvds_rx_inst|altlvds_rx_component|rxreg[1] ,
\lvds_rx_inst|altlvds_rx_component|rxreg[0] }),
	.rx_locked(\lvds_rx_inst|altlvds_rx_component|pll~0 ));
mult mult_inst(
	.clock(\lvds_rx_inst|altlvds_rx_component|rx_outclock ),
	.datab({\lvds_rx_inst|altlvds_rx_component|rxreg[15] ,\lvds_rx_inst|altlvds_rx_component|rxreg[14] ,\lvds_rx_inst|altlvds_rx_component|rxreg[13] ,\lvds_rx_inst|altlvds_rx_component|rxreg[12] ,\lvds_rx_inst|altlvds_rx_component|rxreg[11] ,
\lvds_rx_inst|altlvds_rx_component|rxreg[10] ,\lvds_rx_inst|altlvds_rx_component|rxreg[9] ,\lvds_rx_inst|altlvds_rx_component|rxreg[8] }),
	.dataa({\lvds_rx_inst|altlvds_rx_component|rxreg[7] ,\lvds_rx_inst|altlvds_rx_component|rxreg[6] ,\lvds_rx_inst|altlvds_rx_component|rxreg[5] ,\lvds_rx_inst|altlvds_rx_component|rxreg[4] ,\lvds_rx_inst|altlvds_rx_component|rxreg[3] ,
\lvds_rx_inst|altlvds_rx_component|rxreg[2] ,\lvds_rx_inst|altlvds_rx_component|rxreg[1] ,\lvds_rx_inst|altlvds_rx_component|rxreg[0] }),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.result({\mult_inst|lpm_mult_component|auto_generated|result[15] ,\mult_inst|lpm_mult_component|auto_generated|result[14] ,\mult_inst|lpm_mult_component|auto_generated|result[13] ,\mult_inst|lpm_mult_component|auto_generated|result[12] ,
\mult_inst|lpm_mult_component|auto_generated|result[11] ,\mult_inst|lpm_mult_component|auto_generated|result[10] ,\mult_inst|lpm_mult_component|auto_generated|result[9] ,\mult_inst|lpm_mult_component|auto_generated|result[8] ,
\mult_inst|lpm_mult_component|auto_generated|result[7] ,\mult_inst|lpm_mult_component|auto_generated|result[6] ,\mult_inst|lpm_mult_component|auto_generated|result[5] ,\mult_inst|lpm_mult_component|auto_generated|result[4] ,
\mult_inst|lpm_mult_component|auto_generated|result[3] ,\mult_inst|lpm_mult_component|auto_generated|result[2] ,\mult_inst|lpm_mult_component|auto_generated|result[1] ,\mult_inst|lpm_mult_component|auto_generated|result[0] }));
lvds_tx lvds_tx_inst(
	.pll(\lvds_rx_inst|altlvds_rx_component|pll~ENAOUT1 ),
	.pll1(\lvds_rx_inst|altlvds_rx_component|pll ),
	.pll2(\lvds_rx_inst|altlvds_rx_component|pll~CLK1 ),
	.rx_outclock(\lvds_rx_inst|altlvds_rx_component|rx_outclock ),
	.result_0(\mult_inst|lpm_mult_component|auto_generated|result[0] ),
	.result_1(\mult_inst|lpm_mult_component|auto_generated|result[1] ),
	.result_2(\mult_inst|lpm_mult_component|auto_generated|result[2] ),
	.result_3(\mult_inst|lpm_mult_component|auto_generated|result[3] ),
	.result_4(\mult_inst|lpm_mult_component|auto_generated|result[4] ),
	.result_5(\mult_inst|lpm_mult_component|auto_generated|result[5] ),
	.result_6(\mult_inst|lpm_mult_component|auto_generated|result[6] ),
	.result_7(\mult_inst|lpm_mult_component|auto_generated|result[7] ),
	.result_8(\mult_inst|lpm_mult_component|auto_generated|result[8] ),
	.result_9(\mult_inst|lpm_mult_component|auto_generated|result[9] ),
	.result_10(\mult_inst|lpm_mult_component|auto_generated|result[10] ),
	.result_11(\mult_inst|lpm_mult_component|auto_generated|result[11] ),
	.result_12(\mult_inst|lpm_mult_component|auto_generated|result[12] ),
	.result_13(\mult_inst|lpm_mult_component|auto_generated|result[13] ),
	.result_14(\mult_inst|lpm_mult_component|auto_generated|result[14] ),
	.result_15(\mult_inst|lpm_mult_component|auto_generated|result[15] ),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.tx_out({\lvds_tx_inst|altlvds_tx_component|tx_out[1] ,\lvds_tx_inst|altlvds_tx_component|tx_out[0] }),
	.tx_outclock(\lvds_tx_inst|altlvds_tx_component|tx_outclock ));

// atom is at Pin_N31
stratix_io \rx_data_align~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\rx_data_align~combout ),
	.regout(),
	.ddioregout(),
	.padio(rx_data_align));
// synopsys translate_off
defparam \rx_data_align~I .operation_mode = "input";
defparam \rx_data_align~I .ddio_mode = "none";
defparam \rx_data_align~I .output_register_mode = "none";
defparam \rx_data_align~I .oe_register_mode = "none";
defparam \rx_data_align~I .input_async_reset = "none";
defparam \rx_data_align~I .output_async_reset = "none";
defparam \rx_data_align~I .oe_async_reset = "none";
defparam \rx_data_align~I .input_sync_reset = "none";
defparam \rx_data_align~I .output_sync_reset = "none";
defparam \rx_data_align~I .oe_sync_reset = "none";
defparam \rx_data_align~I .input_power_up = "low";
defparam \rx_data_align~I .output_power_up = "low";
defparam \rx_data_align~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_T36
stratix_io \rx_in[0]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\rx_in[0]~combout ),
	.regout(),
	.ddioregout(),
	.padio(rx_in[0]));
// synopsys translate_off
defparam \rx_in[0]~I .operation_mode = "input";
defparam \rx_in[0]~I .ddio_mode = "none";
defparam \rx_in[0]~I .output_register_mode = "none";
defparam \rx_in[0]~I .oe_register_mode = "none";
defparam \rx_in[0]~I .input_async_reset = "none";
defparam \rx_in[0]~I .output_async_reset = "none";
defparam \rx_in[0]~I .oe_async_reset = "none";
defparam \rx_in[0]~I .input_sync_reset = "none";
defparam \rx_in[0]~I .output_sync_reset = "none";
defparam \rx_in[0]~I .oe_sync_reset = "none";
defparam \rx_in[0]~I .input_power_up = "low";
defparam \rx_in[0]~I .output_power_up = "low";
defparam \rx_in[0]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_T39
stratix_io \rx_in[1]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\rx_in[1]~combout ),
	.regout(),
	.ddioregout(),
	.padio(rx_in[1]));
// synopsys translate_off
defparam \rx_in[1]~I .operation_mode = "input";
defparam \rx_in[1]~I .ddio_mode = "none";
defparam \rx_in[1]~I .output_register_mode = "none";
defparam \rx_in[1]~I .oe_register_mode = "none";
defparam \rx_in[1]~I .input_async_reset = "none";
defparam \rx_in[1]~I .output_async_reset = "none";
defparam \rx_in[1]~I .oe_async_reset = "none";
defparam \rx_in[1]~I .input_sync_reset = "none";
defparam \rx_in[1]~I .output_sync_reset = "none";
defparam \rx_in[1]~I .oe_sync_reset = "none";
defparam \rx_in[1]~I .input_power_up = "low";
defparam \rx_in[1]~I .output_power_up = "low";
defparam \rx_in[1]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_Y38
stratix_io \rx_inclock~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\rx_inclock~combout ),
	.regout(),
	.ddioregout(),
	.padio(rx_inclock));
// synopsys translate_off
defparam \rx_inclock~I .operation_mode = "input";
defparam \rx_inclock~I .ddio_mode = "none";
defparam \rx_inclock~I .output_register_mode = "none";
defparam \rx_inclock~I .oe_register_mode = "none";
defparam \rx_inclock~I .input_async_reset = "none";
defparam \rx_inclock~I .output_async_reset = "none";
defparam \rx_inclock~I .oe_async_reset = "none";
defparam \rx_inclock~I .input_sync_reset = "none";
defparam \rx_inclock~I .output_sync_reset = "none";
defparam \rx_inclock~I .oe_sync_reset = "none";
defparam \rx_inclock~I .input_power_up = "low";
defparam \rx_inclock~I .output_power_up = "low";
defparam \rx_inclock~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_N30
stratix_io \rx_locked~I (
	.datain(\lvds_rx_inst|altlvds_rx_component|pll~0 ),
	.ddiodatain(),
	.oe(vcc),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(rx_locked));
// synopsys translate_off
defparam \rx_locked~I .operation_mode = "output";
defparam \rx_locked~I .ddio_mode = "none";
defparam \rx_locked~I .output_register_mode = "none";
defparam \rx_locked~I .oe_register_mode = "none";
defparam \rx_locked~I .input_async_reset = "none";
defparam \rx_locked~I .output_async_reset = "none";
defparam \rx_locked~I .oe_async_reset = "none";
defparam \rx_locked~I .input_sync_reset = "none";
defparam \rx_locked~I .output_sync_reset = "none";
defparam \rx_locked~I .oe_sync_reset = "none";
defparam \rx_locked~I .input_power_up = "low";
defparam \rx_locked~I .output_power_up = "low";
defparam \rx_locked~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_M34
stratix_io \tx_out[1]~I (
	.datain(\lvds_tx_inst|altlvds_tx_component|tx_out[1] ),
	.ddiodatain(),
	.oe(vcc),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(tx_out[1]));
// synopsys translate_off
defparam \tx_out[1]~I .operation_mode = "output";
defparam \tx_out[1]~I .ddio_mode = "none";
defparam \tx_out[1]~I .output_register_mode = "none";
defparam \tx_out[1]~I .oe_register_mode = "none";
defparam \tx_out[1]~I .input_async_reset = "none";
defparam \tx_out[1]~I .output_async_reset = "none";
defparam \tx_out[1]~I .oe_async_reset = "none";
defparam \tx_out[1]~I .input_sync_reset = "none";
defparam \tx_out[1]~I .output_sync_reset = "none";
defparam \tx_out[1]~I .oe_sync_reset = "none";
defparam \tx_out[1]~I .input_power_up = "low";
defparam \tx_out[1]~I .output_power_up = "low";
defparam \tx_out[1]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_N34
stratix_io \tx_out[0]~I (
	.datain(\lvds_tx_inst|altlvds_tx_component|tx_out[0] ),
	.ddiodatain(),
	.oe(vcc),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(tx_out[0]));
// synopsys translate_off
defparam \tx_out[0]~I .operation_mode = "output";
defparam \tx_out[0]~I .ddio_mode = "none";
defparam \tx_out[0]~I .output_register_mode = "none";
defparam \tx_out[0]~I .oe_register_mode = "none";
defparam \tx_out[0]~I .input_async_reset = "none";
defparam \tx_out[0]~I .output_async_reset = "none";
defparam \tx_out[0]~I .oe_async_reset = "none";
defparam \tx_out[0]~I .input_sync_reset = "none";