gate_sim.do

这个verilog代码是一个输入输出经典的例子。大家一起参考。

source comp_altera_lib.do                                    
source comp_gate.do                                          
echo *** Refreshing library .... 
vlog -work work -refresh                                                                        
onerror {resume}   
vsim +transport_int_delays +transport_path_delays -L stratix work.test_high_speed_io
add wave -noupdate -format Literal /test_high_speed_io/rx_in
add wave -noupdate -format Logic /test_high_speed_io/rx_inclock
add wave -noupdate -format Logic /test_high_speed_io/rx_data_align
add wave -noupdate -format Logic /test_high_speed_io/rx_locked
add wave -noupdate -format Logic /test_high_speed_io/diff_io_top_inst/lvds_rx_inst/pll1
add wave -noupdate -format Literal -radix unsigned /test_high_speed_io/diff_io_top_inst/mult_inst/datab
add wave -noupdate -format Literal -radix unsigned /test_high_speed_io/diff_io_top_inst/mult_inst/dataa
add wave -noupdate -format Literal -radix unsigned /test_high_speed_io/diff_io_top_inst/mult_inst/result
add wave -noupdate -format Literal /test_high_speed_io/tx_out
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {171942 ps}
WaveRestoreZoom {1007865 ps} {1060625 ps}
configure wave -namecolwidth 212
configure wave -valuecolwidth 40
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2                                            
run 1250 ns