ddr_cntl_a_addr_gen_0.v

arm控制FPGA的DDR测试代码

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  / Vendor: Xilinx
// \   \   \/ Version: 1.6
//  \   \    Application : MIG
//  /   /    Filename: ddr_cntl_a_addr_gen_0.v
// /___/   /\ Date Last Modified:  Tue Jul 11 2006
// \   \  /  \ Date Created: Mon May 2 2005
//  \___\/\___\
// Device: Spartan-3/3e
// Design Name: DDR1_S3/S3e
// Description: It generates address and burst done signal for the test bench.
///////////////////////////////////////////////////////////////////////////////

`include "ddr_cntl_a_parameters_0.v"

`timescale 1ns/100ps

module ddr_cntl_a_addr_gen_0(
                clk,
	        rst,
	        addr_rst,  
	        addr_inc, 
	        addr_out,  
	        test_cnt_ena,  
	        burst_done,  
	        cnt_roll 
                );

   input        clk;               
   input        rst;
   input        addr_rst;
   input        addr_inc;
   input        test_cnt_ena;
   
     output [((`row_address + `col_ap_width + `bank_address)-1):0] addr_out;
      
   output       burst_done;
   output       cnt_roll;
   
   reg          cnt_roll;
   reg [7:0]    column_counter;
   reg [1:0]    cnt;
   reg          burst_done_reg;
   reg          burst_done_1_reg;

   reg          cnt_roll_p;
   reg          cnt_roll_p2;
   
   wire [`bank_address-1:0]   ba_count;


   
assign ba_count       = {{`bank_address-1{1'b0}},1'b0}; 
assign addr_out       = {{`row_address-2{1'b0}},2'b10,{`col_ap_width -8{1'b0}},column_counter, ba_count};



assign burst_done     = burst_done_1_reg;




always @ (posedge clk)
begin
   if (rst == 1'b1 || addr_rst == 1'b1)
     begin
        column_counter <= 8'b0;
        cnt <= 2'b0;
     end


       else if (addr_inc == 1'b1)
     begin
        if (cnt == 2'b01)
          cnt <= 2'b0;
        else
          cnt <= cnt + 1'b1;
        if ((test_cnt_ena == 1'b1) && (cnt == 2'b01))

          begin
           if (column_counter == 8'b00010000)
              column_counter <= 8'b0;
           else 
                column_counter <= column_counter + 4'h4;  
          end
        else 
            column_counter <= column_counter;
     end
end



always @ (posedge clk)
begin


  burst_done_reg <= (!rst && column_counter[4]);
   


end

always @ (posedge clk)
begin
 burst_done_1_reg <= (!rst && burst_done_reg );
end



always @ (posedge clk)
begin


      cnt_roll_p <= (!rst && column_counter[3] && column_counter[2] && !column_counter[1] && !column_counter[0]); //BL = 4



end


always @ (posedge clk)
begin
  if (rst == 1'b1)
    begin
     cnt_roll_p2 <= 1'b0;
     cnt_roll    <= 1'b0;
    end
  else
    begin
     cnt_roll_p2  <= cnt_roll_p;
     cnt_roll     <= cnt_roll_p2;
    end
end



endmodule