ddr_cntl_a_parameters_0.v

arm控制FPGA的DDR测试代码

//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  / Vendor: Xilinx
// \   \   \/ Version: 1.6
//  \   \    Application : MIG
//  /   /    Filename: ddr_cntl_a_parameters_0.v
// /___/   /\ Date Last Modified:  Tue Jul 11 2006
// \   \  /  \ Date Created: Mon May 2 2005
//  \___\/\___\
// Device: Spartan-3/3e
// Design Name: DDR1_S3/S3e
// Description: This module contains the parameters used in the design
///////////////////////////////////////////////////////////////////////////////

`define    data_width                               32
`define    data_strobe_width                        4
`define    data_mask_width                          4
`define    clk_width                                2
`define    fifo_16                                  2
`define    ReadEnable                               1
`define    row_address                              13
`define    column_address                           9
`define    bank_address                             2
`define    memory_width                             8
`define    DatabitsPerReadClock                     8
`define    DatabitsPerMask                          8
`define    no_of_cs                                 1
`define    data_mask                                1
`define    mask_disable                             0
`define    RESET                                    0
`define    dimm                                     0
`define    comp                                     1
`define    cke_width                                1
`define    registered                               0
`define    unbuffered                               1
`define    col_ap_width                             11
`define    write_pipe_itr                           1
`define    tb_enable                                1
`define    tb_disable                               0
`define    dcm_enable                               1
`define    dcm_disable                              0
`define    write_pipeline                           4
`define    top_bottom                                0
`define    left_right                                1
`define    foundation_ise                           1
`define   burst_length                                     3'b010
`define   burst_type                                       1'b0
`define   cas_latency_value                                3'b010
`define   Operating_mode                                   5'b00000
`define    load_mode_register       13'b0000000100010
`define    chip_address                     1
`define    rcd_count_value                 3'b010
`define    ras_count_value                 4'b0101
`define    mrd_count_value                 1'b0
`define    rp_count_value                  3'b010
`define    rfc_count_value                 6'b001001
`define    twr_count_value                 3'b110
`define    twtr_count_value                3'b100
`define     max_ref_width                   11
`define    max_ref_cnt                  11'b10000000001


`timescale 1ns/100ps 

`define rtp_count_value        2'b01    // read to precharge = (1 (for BL=4)/ 3(for BL=8)) from DDR2
`define wtp_count_value	       4'b1000    // write to precharge = (8 (for BL=4)/ 10(for BL=8)) from DDR2
`define wr_to_rd_count_value   4'b0110    // write to read command time = (6 (for Bl =4)/ 8(for BL=8)) from DDR2                        
`define Phy_Mode              1'b1    // 1- direct clocking, 0- local clocking