ddr_cntl_a.v

arm控制FPGA的DDR测试代码

//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  / Vendor: Xilinx
// \   \   \/ Version: 1.6
//  \   \    Application : MIG
//  /   /    Filename: ddr_cntl_a.v
// /___/   /\ Date Last Modified:  Tue Jul 11 2006
// \   \  /  \ Date Created: Mon May 2 2005
//  \___\/\___\
// Device: Spartan-3/3e
// Design Name: DDR1_S3/S3e
// Description: This module contains the instantiations for 
//		    -infrastructure_top and
//              -main modules
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns/100ps

module ddr_cntl_a 
     (
	cntrl0_DDR_DQ,
cntrl0_DDR_A,
cntrl0_DDR_BA,
cntrl0_DDR_CKE,
cntrl0_DDR_CS_N,
cntrl0_DDR_RAS_N,
cntrl0_DDR_CAS_N,
cntrl0_DDR_WE_N,
cntrl0_DDR_DM,
cntrl0_rst_dqs_div_in,
cntrl0_rst_dqs_div_out,
SYS_CLKb,
SYS_CLK,
cntrl0_led_error_output1,
reset_in,
cntrl0_DDR_DQS,
cntrl0_DDR_CK,
cntrl0_DDR_CK_N
      ); 
//Input/Output declarations


inout [31:0] cntrl0_DDR_DQ;
output [12:0] cntrl0_DDR_A;
output [1:0] cntrl0_DDR_BA;
output  cntrl0_DDR_CKE;
output  cntrl0_DDR_CS_N;
output  cntrl0_DDR_RAS_N;
output  cntrl0_DDR_CAS_N;
output  cntrl0_DDR_WE_N;
output [3:0] cntrl0_DDR_DM;
input  cntrl0_rst_dqs_div_in;
output  cntrl0_rst_dqs_div_out;
input  SYS_CLKb;
input  SYS_CLK;
output  cntrl0_led_error_output1;
input  reset_in;
inout [3:0] cntrl0_DDR_DQS;
output [1:0] cntrl0_DDR_CK;
output [1:0] cntrl0_DDR_CK_N;

wire wait_200us;
wire clk_0;
wire clk90_0;

wire sys_rst;
wire sys_rst90;
wire sys_rst180;
wire sys_rst270;
wire [4:0] delay_sel_tb;
wire [4:0] delay_sel_val; 
wire clk_out;
wire clk90_out;

assign    clk_out = clk_0;  // for no tb
assign    clk90_out = clk90_0;  // for no tb




//----  Component instantiations  ---- 


					ddr_cntl_a_main_0     main_00(.DDR_DQ	(cntrl0_DDR_DQ),
.DDR_A	(cntrl0_DDR_A),
.DDR_BA	(cntrl0_DDR_BA),
.DDR_CKE	(cntrl0_DDR_CKE),
.DDR_CS_N	(cntrl0_DDR_CS_N),
.DDR_RAS_N	(cntrl0_DDR_RAS_N),
.DDR_CAS_N	(cntrl0_DDR_CAS_N),
.DDR_WE_N	(cntrl0_DDR_WE_N),
.DDR_DM	(cntrl0_DDR_DM),
.rst_dqs_div_in	(cntrl0_rst_dqs_div_in),
.rst_dqs_div_out	(cntrl0_rst_dqs_div_out),
.led_error_output1	(cntrl0_led_error_output1),
.DDR_DQS	(cntrl0_DDR_DQS),
.DDR_CK	(cntrl0_DDR_CK),
.DDR_CK_N	(cntrl0_DDR_CK_N),

					.wait_200us	(wait_200us),
					.clk_int	(clk_0),
					.clk90_int	(clk90_0),
					.sys_rst_val	(sys_rst),
					.sys_rst90_val	(sys_rst90),
					.sys_rst180_val	(sys_rst180),
					.sys_rst270_val	(sys_rst270),
					.delay_sel_val	(delay_sel_val)

);


ddr_cntl_a_infrastructure_top infrastructure_top0
                                       (
				       .SYS_CLKb	(SYS_CLKb),
.SYS_CLK	(SYS_CLK),
.reset_in	(reset_in),	   

					.wait_200us	(wait_200us),
					.delay_sel_val1_val_tb(delay_sel_tb),
					.delay_sel_val1_val_rl(delay_sel_val), 
					.sys_rst_val	(sys_rst),
					.sys_rst90_val	(sys_rst90),
					.clk_int_val	(clk_0),
					.clk90_int_val	(clk90_0),
					.sys_rst180_val	(sys_rst180),
					.sys_rst270_val	(sys_rst270)

                                       );

endmodule