ise_run.txt

arm控制FPGA的DDR测试代码

set -tmpdir ../synth/__projnav 
set -xsthdpdir ../synth/xst
run -ifn ../synth/ddr_cntl_a.prj -ifmt mixed -ofn ddr_cntl_a -ofmt NGC -p xc3s4000-4fg900 -top ddr_cntl_a -opt_mode Speed -opt_level 2 -uc ../synth/mem_interface_top.xcf -lso ../synth/ddr_cntl_a.lso -keep_hierarchy YES -glob_opt AllClockNets -rtlview Yes -read_cores YES -write_timing_constraints NO -cross_clock_analysis NO -hierarchy_separator / -bus_delimiter [] -case maintain -slice_utilization_ratio 100 -verilog2001 YES -vlgincdir  -fsm_extract YES -fsm_encoding Auto -fsm_style lut -ram_extract Yes -ram_style Auto -rom_extract Yes -rom_style Auto -mux_extract YES -mux_style Auto -decoder_extract YES -priority_extract YES -shreg_extract YES -shift_extract YES -xor_collapse YES -resource_sharing YES -mult_style auto -iobuf YES -max_fanout 500 -bufg 8 -equivalent_register_removal NO -register_balancing YES -slice_packing NO -optimize_primitives NO -tristate2logic No -iob false -slice_utilization_ratio_maxmargin 5
quit