📄 ddr_cntl_a.ucf
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INST "infrastructure_top0/cal_top0/tap_dly0/r16" RLOC=X0Y2;
INST "infrastructure_top0/cal_top0/tap_dly0/r16" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r17" RLOC=X0Y2;
INST "infrastructure_top0/cal_top0/tap_dly0/r17" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r18" RLOC=X0Y3;
INST "infrastructure_top0/cal_top0/tap_dly0/r18" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r19" RLOC=X0Y3;
INST "infrastructure_top0/cal_top0/tap_dly0/r19" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r20" RLOC=X1Y2;
INST "infrastructure_top0/cal_top0/tap_dly0/r20" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r21" RLOC=X1Y2;
INST "infrastructure_top0/cal_top0/tap_dly0/r21" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r22" RLOC=X1Y3;
INST "infrastructure_top0/cal_top0/tap_dly0/r22" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r23" RLOC=X1Y3;
INST "infrastructure_top0/cal_top0/tap_dly0/r23" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r24" RLOC=X0Y0;
INST "infrastructure_top0/cal_top0/tap_dly0/r24" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r25" RLOC=X0Y0;
INST "infrastructure_top0/cal_top0/tap_dly0/r25" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r26" RLOC=X0Y1;
INST "infrastructure_top0/cal_top0/tap_dly0/r26" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r27" RLOC=X0Y1;
INST "infrastructure_top0/cal_top0/tap_dly0/r27" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r28" RLOC=X1Y0;
INST "infrastructure_top0/cal_top0/tap_dly0/r28" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r29" RLOC=X1Y0;
INST "infrastructure_top0/cal_top0/tap_dly0/r29" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r30" RLOC=X1Y1;
INST "infrastructure_top0/cal_top0/tap_dly0/r30" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r31" RLOC=X1Y1;
INST "infrastructure_top0/cal_top0/tap_dly0/r31" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
#######################################################################################################################
# BEL constraints for luts in tap delay ckt #
#######################################################################################################################
INST "infrastructure_top0/cal_top0/tap_dly0/l0" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l1" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l2" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l3" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l4" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l5" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l6" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l7" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l8" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l9" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l10" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l11" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l12" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l13" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l14" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l15" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l16" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l17" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l18" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l19" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l20" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l21" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l22" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l23" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l24" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l25" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l26" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l27" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l28" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l29" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l30" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l31" BEL= F;
######################################################################################
##### constraints to have the inverter connetion wire length to be the same ########
###### the following constraints are independent of frequency ######################
######################################################################################
###### maxdelay of 400 ps will not be met. This constraint is just to get a better delay####
NET "infrastructure_top0/cal_top0/tap_dly0/tap[7]" MAXDELAY = 400ps;
NET "infrastructure_top0/cal_top0/tap_dly0/tap[15]" MAXDELAY = 400ps;
NET "infrastructure_top0/cal_top0/tap_dly0/tap[23]" MAXDELAY = 400ps;
INST "main_00/top0/controller0/rst_iob_out" IOB = TRUE;
##################################################################
##### constraints from the dqs pin ########
##################################################################
###### maxdelay of 460 ps will not be met. This constraint is just to get a better delay####
###### The reported delay will be in the range of 500 to 600 ps####
NET "main_00/top0/dqs_int_delay_in*" MAXDELAY = 460ps;
###### maxdelay of 160 ps will not be met. This constraint is just to get a better delay####
###### The reported delay will be in the range of 200 to 360 ps####
NET "main_00/top0/data_path0/data_read_controller0/dqs_delay*_col*/delay*" MAXDELAY = 160ps;
###################################################################################################
######constraint to place flop1 and flop2 close togather for the calibration logic ###############
###################################################################################################
NET "infrastructure_top0/cal_top0/tap_dly0/flop1[*]" MAXDELAY = 3000ps;
#######################################################################################################################
# Area Group Constraint For tap_dly and cal_ctl module #
#######################################################################################################################
INST "infrastructure_top0/cal_top0/cal_ctl0" AREA_GROUP = cal_ctl;
INST "infrastructure_top0/cal_top0/tap_dly0" AREA_GROUP = cal_ctl;
AREA_GROUP "cal_ctl" RANGE = SLICE_X8Y92:SLICE_X17Y105;
AREA_GROUP "cal_ctl" GROUP = CLOSED;
#********************************************************************#
# CONTROLLER 0 #
#********************************************************************#
############################################################################
# I/O STANDARDS #
############################################################################
NET "cntrl0_DDR_DQ[*]" IOSTANDARD = SSTL2_II;
NET "cntrl0_DDR_A[*]" IOSTANDARD = SSTL2_II;
NET "cntrl0_DDR_BA[*]" IOSTANDARD = SSTL2_II;
NET "cntrl0_DDR_CKE" IOSTANDARD = SSTL2_II;
NET "cntrl0_DDR_CS_N" IOSTANDARD = SSTL2_II;
NET "cntrl0_DDR_RAS_N" IOSTANDARD = SSTL2_II;
NET "cntrl0_DDR_CAS_N" IOSTANDARD = SSTL2_II;
NET "cntrl0_DDR_WE_N" IOSTANDARD = SSTL2_II;
NET "cntrl0_DDR_DM[*]" IOSTANDARD = SSTL2_II;
NET "cntrl0_rst_dqs_div_in" IOSTANDARD = SSTL2_II;
NET "cntrl0_rst_dqs_div_out" IOSTANDARD = SSTL2_II;
NET "SYS_CLKb" IOSTANDARD = LVDS_25;
NET "SYS_CLK" IOSTANDARD = LVDS_25;
NET "cntrl0_led_error_output1" IOSTANDARD = SSTL2_I;
NET "reset_in" IOSTANDARD = LVCMOS25;
NET "cntrl0_DDR_DQS[*]" IOSTANDARD = SSTL2_II;
NET "cntrl0_DDR_CK[*]" IOSTANDARD = SSTL2_II;
NET "cntrl0_DDR_CK_N[*]" IOSTANDARD = SSTL2_II;
############################################################################
# IO Signals Registering Constraints #
############################################################################
INST "main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob*" IOB = TRUE;
INST "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob*" IOB = TRUE;
INST "main_00/top0/controller0/rst_iob_out" IOB = TRUE;
INST "main_00/top0/iobs0/controller_iobs0/iob_addr*" IOB = TRUE;
INST "main_00/top0/iobs0/controller_iobs0/iob_ba*" IOB = TRUE;
INST "main_00/top0/iobs0/controller_iobs0/iob_rasb" IOB = TRUE;
INST "main_00/top0/iobs0/controller_iobs0/iob_casb" IOB = TRUE;
INST "main_00/top0/iobs0/controller_iobs0/iob_web" IOB = TRUE;
INST "main_00/top0/iobs0/controller_iobs0/iob_cke" IOB = TRUE;
############################################################################
# Banks 03
# Pin Location Constraints for System clock signals
############################################################################
NET "SYS_CLKb" LOC = "B15";
NET "SYS_CLK" LOC = "A15";
############################################################################
# Banks 7
# Pin Location Constraints for Clock,Masks, Address, and Controls
############################################################################
NET "cntrl0_DDR_CK[0]" LOC = "J2" ;
NET "cntrl0_DDR_CK_N[0]" LOC = "J1" ;
NET "cntrl0_DDR_CK[1]" LOC = "J5" ;
NET "cntrl0_DDR_CK_N[1]" LOC = "J4" ;
NET "cntrl0_DDR_DM[0]" LOC = "R6" ;
NET "cntrl0_DDR_DM[1]" LOC = "M3" ;
NET "cntrl0_DDR_DM[2]" LOC = "K7" ;
NET "cntrl0_DDR_DM[3]" LOC = "H2" ;
NET "cntrl0_DDR_A[12]" LOC = "H4" ;
NET "cntrl0_DDR_A[11]" LOC = "H3" ;
NET "cntrl0_DDR_A[10]" LOC = "G6" ;
NET "cntrl0_DDR_A[9]" LOC = "H7" ;
NET "cntrl0_DDR_A[8]" LOC = "G2" ;
NET "cntrl0_DDR_A[7]" LOC = "G1" ;
NET "cntrl0_DDR_A[6]" LOC = "G4" ;
NET "cntrl0_DDR_A[5]" LOC = "G3" ;
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