script_pre1.tcl

arm控制FPGA的DDR测试代码

new_project -name "project_1" -folder "../synth" -createimpl_name "rev_1"
        add_input_file {
../rtl/ddr_cntl_a.v
../rtl/ddr_cntl_a_addr_gen_0.v
../rtl/ddr_cntl_a_cal_ctl_0.v
../rtl/ddr_cntl_a_cal_top.v
../rtl/ddr_cntl_a_clk_dcm.v
../rtl/ddr_cntl_a_cmd_fsm_0.v
../rtl/ddr_cntl_a_cmp_data_0.v
../rtl/ddr_cntl_a_controller_0.v
../rtl/ddr_cntl_a_controller_iobs_0.v
../rtl/ddr_cntl_a_data_path_0.v
../rtl/ddr_cntl_a_data_path_iobs_0.v
../rtl/ddr_cntl_a_data_path_rst.v
../rtl/ddr_cntl_a_data_read_0.v
../rtl/ddr_cntl_a_data_read_controller_0.v
../rtl/ddr_cntl_a_data_write_0.v
../rtl/ddr_cntl_a_ddr1_dm_0.v
../rtl/ddr_cntl_a_ddr1_test_bench_0.v
../rtl/ddr_cntl_a_dqs_delay.v
../rtl/ddr_cntl_a_fifo_0_wr_en_0.v
../rtl/ddr_cntl_a_fifo_1_wr_en_0.v
../rtl/ddr_cntl_a_glbl.v
../rtl/ddr_cntl_a_infrastructure.v
../rtl/ddr_cntl_a_infrastructure_iobs_0.v
../rtl/ddr_cntl_a_infrastructure_top.v
../rtl/ddr_cntl_a_iobs_0.v
../rtl/ddr_cntl_a_lfsr32_0.v
../rtl/ddr_cntl_a_main_0.v
../rtl/ddr_cntl_a_mybufg_0.v
../rtl/ddr_cntl_a_parameters_0.v
../rtl/ddr_cntl_a_RAM8D_0.v
../rtl/ddr_cntl_a_rd_gray_cntr.v
../rtl/ddr_cntl_a_s3_ddr_iob.v
../rtl/ddr_cntl_a_s3_dqs_iob.v
../rtl/ddr_cntl_a_tap_dly_0.v
../rtl/ddr_cntl_a_top_0.v
../rtl/ddr_cntl_a_wr_gray_cntr.v
}
 setup_design -frequency=133