ddr_cntl_a_data_path_iobs_0.v

arm控制FPGA的DDR测试代码

      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob11 
				(
      				.ddr_dq_inout       (ddr_dq[11]), 
      				.write_data_falling (write_data_falling[11]), 
      				.write_data_rising  (write_data_rising[11]),
      				.read_data_in       (ddr_dq_in[11]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob12 
				(
      				.ddr_dq_inout       (ddr_dq[12]), 
      				.write_data_falling (write_data_falling[12]), 
      				.write_data_rising  (write_data_rising[12]),
      				.read_data_in       (ddr_dq_in[12]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob13 
				(
      				.ddr_dq_inout       (ddr_dq[13]), 
      				.write_data_falling (write_data_falling[13]), 
      				.write_data_rising  (write_data_rising[13]),
      				.read_data_in       (ddr_dq_in[13]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob14 
				(
      				.ddr_dq_inout       (ddr_dq[14]), 
      				.write_data_falling (write_data_falling[14]), 
      				.write_data_rising  (write_data_rising[14]),
      				.read_data_in       (ddr_dq_in[14]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob15 
				(
      				.ddr_dq_inout       (ddr_dq[15]), 
      				.write_data_falling (write_data_falling[15]), 
      				.write_data_rising  (write_data_rising[15]),
      				.read_data_in       (ddr_dq_in[15]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob16 
				(
      				.ddr_dq_inout       (ddr_dq[16]), 
      				.write_data_falling (write_data_falling[16]), 
      				.write_data_rising  (write_data_rising[16]),
      				.read_data_in       (ddr_dq_in[16]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob17 
				(
      				.ddr_dq_inout       (ddr_dq[17]), 
      				.write_data_falling (write_data_falling[17]), 
      				.write_data_rising  (write_data_rising[17]),
      				.read_data_in       (ddr_dq_in[17]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob18 
				(
      				.ddr_dq_inout       (ddr_dq[18]), 
      				.write_data_falling (write_data_falling[18]), 
      				.write_data_rising  (write_data_rising[18]),
      				.read_data_in       (ddr_dq_in[18]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob19 
				(
      				.ddr_dq_inout       (ddr_dq[19]), 
      				.write_data_falling (write_data_falling[19]), 
      				.write_data_rising  (write_data_rising[19]),
      				.read_data_in       (ddr_dq_in[19]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob20 
				(
      				.ddr_dq_inout       (ddr_dq[20]), 
      				.write_data_falling (write_data_falling[20]), 
      				.write_data_rising  (write_data_rising[20]),
      				.read_data_in       (ddr_dq_in[20]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob21 
				(
      				.ddr_dq_inout       (ddr_dq[21]), 
      				.write_data_falling (write_data_falling[21]), 
      				.write_data_rising  (write_data_rising[21]),
      				.read_data_in       (ddr_dq_in[21]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob22 
				(
      				.ddr_dq_inout       (ddr_dq[22]), 
      				.write_data_falling (write_data_falling[22]), 
      				.write_data_rising  (write_data_rising[22]),
      				.read_data_in       (ddr_dq_in[22]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob23 
				(
      				.ddr_dq_inout       (ddr_dq[23]), 
      				.write_data_falling (write_data_falling[23]), 
      				.write_data_rising  (write_data_rising[23]),
      				.read_data_in       (ddr_dq_in[23]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob24 
				(
      				.ddr_dq_inout       (ddr_dq[24]), 
      				.write_data_falling (write_data_falling[24]), 
      				.write_data_rising  (write_data_rising[24]),
      				.read_data_in       (ddr_dq_in[24]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob25 
				(
      				.ddr_dq_inout       (ddr_dq[25]), 
      				.write_data_falling (write_data_falling[25]), 
      				.write_data_rising  (write_data_rising[25]),
      				.read_data_in       (ddr_dq_in[25]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob26 
				(
      				.ddr_dq_inout       (ddr_dq[26]), 
      				.write_data_falling (write_data_falling[26]), 
      				.write_data_rising  (write_data_rising[26]),
      				.read_data_in       (ddr_dq_in[26]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob27 
				(
      				.ddr_dq_inout       (ddr_dq[27]), 
      				.write_data_falling (write_data_falling[27]), 
      				.write_data_rising  (write_data_rising[27]),
      				.read_data_in       (ddr_dq_in[27]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob28 
				(
      				.ddr_dq_inout       (ddr_dq[28]), 
      				.write_data_falling (write_data_falling[28]), 
      				.write_data_rising  (write_data_rising[28]),
      				.read_data_in       (ddr_dq_in[28]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob29 
				(
      				.ddr_dq_inout       (ddr_dq[29]), 
      				.write_data_falling (write_data_falling[29]), 
      				.write_data_rising  (write_data_rising[29]),
      				.read_data_in       (ddr_dq_in[29]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob30 
				(
      				.ddr_dq_inout       (ddr_dq[30]), 
      				.write_data_falling (write_data_falling[30]), 
      				.write_data_rising  (write_data_rising[30]),
      				.read_data_in       (ddr_dq_in[30]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob31 
				(
      				.ddr_dq_inout       (ddr_dq[31]), 
      				.write_data_falling (write_data_falling[31]), 
      				.write_data_rising  (write_data_rising[31]),
      				.read_data_in       (ddr_dq_in[31]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );

                        		     

endmodule