📄 _pace.ucf
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## constraints for bit cntrl0_DDR_DQ, 18, location in tile: 0
INST "main_00/top0/data_path0/data_read0/strobe2/fifo_bit2" LOC = SLICE_X0Y132;
INST "main_00/top0/data_path0/data_read0/strobe2_n/fifo_bit2" LOC = SLICE_X0Y133;
#############################################################
## constraints for bit cntrl0_DDR_DQS, 2, location in tile: 0
## LUT location constraints for col 0
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col0/one" LOC = SLICE_X2Y135;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col0/one" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col0/two" LOC = SLICE_X2Y135;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col0/two" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col0/three" LOC = SLICE_X2Y134;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col0/three" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col0/four" LOC = SLICE_X2Y134;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col0/four" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col0/five" LOC = SLICE_X3Y135;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col0/five" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col0/six" LOC = SLICE_X3Y134;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col0/six" BEL = G;
## LUT location constraints for col 1
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col1/one" LOC = SLICE_X0Y135;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col1/one" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col1/two" LOC = SLICE_X0Y135;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col1/two" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col1/three" LOC = SLICE_X0Y134;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col1/three" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col1/four" LOC = SLICE_X0Y134;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col1/four" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col1/five" LOC = SLICE_X1Y135;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col1/five" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col1/six" LOC = SLICE_X1Y134;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col1/six" BEL = G;
########################WRITE ADD & WRITE_EN##########
INST "main_00/top0/data_path0/data_read_controller0/fifo_20_wr_addr_inst/bit0" LOC = SLICE_X1Y130;
INST "main_00/top0/data_path0/data_read_controller0/fifo_20_wr_addr_inst/bit1" LOC = SLICE_X1Y130;
INST "main_00/top0/data_path0/data_read_controller0/fifo_20_wr_addr_inst/bit2" LOC = SLICE_X1Y131;
INST "main_00/top0/data_path0/data_read_controller0/fifo_20_wr_addr_inst/bit3" LOC = SLICE_X1Y131;
INST "main_00/top0/data_path0/data_read_controller0/fifo_21_wr_addr_inst/bit0" LOC = SLICE_X3Y130;
INST "main_00/top0/data_path0/data_read_controller0/fifo_21_wr_addr_inst/bit1" LOC = SLICE_X3Y130;
INST "main_00/top0/data_path0/data_read_controller0/fifo_21_wr_addr_inst/bit2" LOC = SLICE_X3Y131;
INST "main_00/top0/data_path0/data_read_controller0/fifo_21_wr_addr_inst/bit3" LOC = SLICE_X3Y131;
INST "main_00/top0/data_path0/data_read_controller0/fifo_20_wr_en_inst" LOC = SLICE_X1Y133;
INST "main_00/top0/data_path0/data_read_controller0/fifo_21_wr_en_inst" LOC = SLICE_X3Y133;
#############################################################
## constraints for bit cntrl0_DDR_DQ, 21, location in tile: 1
INST "main_00/top0/data_path0/data_read0/strobe2/fifo_bit5" LOC = SLICE_X2Y136;
INST "main_00/top0/data_path0/data_read0/strobe2_n/fifo_bit5" LOC = SLICE_X2Y137;
#############################################################
## constraints for bit cntrl0_DDR_DQ, 20, location in tile: 0
INST "main_00/top0/data_path0/data_read0/strobe2/fifo_bit4" LOC = SLICE_X0Y136;
INST "main_00/top0/data_path0/data_read0/strobe2_n/fifo_bit4" LOC = SLICE_X0Y137;
#############################################################
## constraints for bit cntrl0_DDR_DQ, 23, location in tile: 1
INST "main_00/top0/data_path0/data_read0/strobe2/fifo_bit7" LOC = SLICE_X2Y138;
INST "main_00/top0/data_path0/data_read0/strobe2_n/fifo_bit7" LOC = SLICE_X2Y139;
#############################################################
## constraints for bit cntrl0_DDR_DQ, 22, location in tile: 0
INST "main_00/top0/data_path0/data_read0/strobe2/fifo_bit6" LOC = SLICE_X0Y138;
INST "main_00/top0/data_path0/data_read0/strobe2_n/fifo_bit6" LOC = SLICE_X0Y139;
#############################################################
## constraints for bit cntrl0_DDR_DQ, 25, location in tile: 1
INST "main_00/top0/data_path0/data_read0/strobe3/fifo_bit1" LOC = SLICE_X2Y142;
INST "main_00/top0/data_path0/data_read0/strobe3_n/fifo_bit1" LOC = SLICE_X2Y143;
#############################################################
## constraints for bit cntrl0_DDR_DQ, 24, location in tile: 0
INST "main_00/top0/data_path0/data_read0/strobe3/fifo_bit0" LOC = SLICE_X0Y142;
INST "main_00/top0/data_path0/data_read0/strobe3_n/fifo_bit0" LOC = SLICE_X0Y143;
#############################################################
## constraints for bit cntrl0_DDR_DQ, 27, location in tile: 1
INST "main_00/top0/data_path0/data_read0/strobe3/fifo_bit3" LOC = SLICE_X2Y144;
INST "main_00/top0/data_path0/data_read0/strobe3_n/fifo_bit3" LOC = SLICE_X2Y145;
#############################################################
## constraints for bit cntrl0_DDR_DQ, 26, location in tile: 0
INST "main_00/top0/data_path0/data_read0/strobe3/fifo_bit2" LOC = SLICE_X0Y144;
INST "main_00/top0/data_path0/data_read0/strobe3_n/fifo_bit2" LOC = SLICE_X0Y145;
#############################################################
## constraints for bit cntrl0_DDR_DQS, 3, location in tile: 0
## LUT location constraints for col 0
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col0/one" LOC = SLICE_X2Y147;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col0/one" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col0/two" LOC = SLICE_X2Y147;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col0/two" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col0/three" LOC = SLICE_X2Y146;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col0/three" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col0/four" LOC = SLICE_X2Y146;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col0/four" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col0/five" LOC = SLICE_X3Y147;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col0/five" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col0/six" LOC = SLICE_X3Y146;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col0/six" BEL = G;
## LUT location constraints for col 1
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col1/one" LOC = SLICE_X0Y147;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col1/one" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col1/two" LOC = SLICE_X0Y147;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col1/two" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col1/three" LOC = SLICE_X0Y146;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col1/three" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col1/four" LOC = SLICE_X0Y146;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col1/four" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col1/five" LOC = SLICE_X1Y147;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col1/five" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col1/six" LOC = SLICE_X1Y146;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col1/six" BEL = G;
########################WRITE ADD & WRITE_EN##########
INST "main_00/top0/data_path0/data_read_controller0/fifo_30_wr_addr_inst/bit0" LOC = SLICE_X1Y142;
INST "main_00/top0/data_path0/data_read_controller0/fifo_30_wr_addr_inst/bit1" LOC = SLICE_X1Y142;
INST "main_00/top0/data_path0/data_read_controller0/fifo_30_wr_addr_inst/bit2" LOC = SLICE_X1Y143;
INST "main_00/top0/data_path0/data_read_controller0/fifo_30_wr_addr_inst/bit3" LOC = SLICE_X1Y143;
INST "main_00/top0/data_path0/data_read_controller0/fifo_31_wr_addr_inst/bit0" LOC = SLICE_X3Y142;
INST "main_00/top0/data_path0/data_read_controller0/fifo_31_wr_addr_inst/bit1" LOC = SLICE_X3Y142;
INST "main_00/top0/data_path0/data_read_controller0/fifo_31_wr_addr_inst/bit2" LOC = SLICE_X3Y143;
INST "main_00/top0/data_path0/data_read_controller0/fifo_31_wr_addr_inst/bit3" LOC = SLICE_X3Y143;
INST "main_00/top0/data_path0/data_read_controller0/fifo_30_wr_en_inst" LOC = SLICE_X1Y145;
INST "main_00/top0/data_path0/data_read_controller0/fifo_31_wr_en_inst" LOC = SLICE_X3Y145;
#############################################################
## constraints for bit cntrl0_DDR_DQ, 29, location in tile: 1
INST "main_00/top0/data_path0/data_read0/strobe3/fifo_bit5" LOC = SLICE_X2Y148;
INST "main_00/top0/data_path0/data_read0/strobe3_n/fifo_bit5" LOC = SLICE_X2Y149;
#############################################################
## constraints for bit cntrl0_DDR_DQ, 28, location in tile: 0
INST "main_00/top0/data_path0/data_read0/strobe3/fifo_bit4" LOC = SLICE_X0Y148;
INST "main_00/top0/data_path0/data_read0/strobe3_n/fifo_bit4" LOC = SLICE_X0Y149;
#############################################################
## constraints for bit cntrl0_DDR_DQ, 30, location in tile: 0
INST "main_00/top0/data_path0/data_read0/strobe3/fifo_bit6" LOC = SLICE_X0Y150;
INST "main_00/top0/data_path0/data_read0/strobe3_n/fifo_bit6" LOC = SLICE_X0Y151;
#############################################################
## constraints for bit cntrl0_DDR_DQ, 31, location in tile: 1
INST "main_00/top0/data_path0/data_read0/strobe3/fifo_bit7" LOC = SLICE_X2Y154;
INST "main_00/top0/data_path0/data_read0/strobe3_n/fifo_bit7" LOC = SLICE_X2Y155;
#############################################################
## constraints for bit cntrl0_rst_dqs_div_in, 1, location in tile: 1
## LUT location constraints for col 1
INST "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/one" LOC = SLICE_X0Y125;
INST "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/one" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/two" LOC = SLICE_X0Y124;
INST "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/two" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/three" LOC = SLICE_X0Y125;
INST "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/three" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/four" LOC = SLICE_X1Y124;
INST "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/four" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/five" LOC = SLICE_X1Y124;
INST "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/five" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/six" LOC = SLICE_X1Y125;
INST "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/six" BEL = G;
#############################################################
## constraints for bit cntrl0_rst_dqs_div_out, 1, location in tile: 1
#################################################################################
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "cntrl0_DDR_A[0]" LOC = "T7" ;
NET "cntrl0_DDR_A[10]" LOC = "V4" ;
NET "cntrl0_DDR_A[11]" LOC = "W5" ;
NET "cntrl0_DDR_A[12]" LOC = "V6" ;
NET "cntrl0_DDR_A[1]" LOC = "T10" ;
NET "cntrl0_DDR_A[2]" LOC = "T9" ;
NET "cntrl0_DDR_A[3]" LOC = "U3" ;
NET "cntrl0_DDR_A[4]" LOC = "U2" ;
NET "cntrl0_DDR_A[5]" LOC = "U7" ;
NET "cntrl0_DDR_A[6]" LOC = "U6" ;
NET "cntrl0_DDR_A[7]" LOC = "V2" ;
NET "cntrl0_DDR_A[8]" LOC = "V1" ;
NET "cntrl0_DDR_A[9]" LOC = "V5" ;
NET "cntrl0_DDR_BA[0]" LOC = "T5" ;
NET "cntrl0_DDR_BA[1]" LOC = "T8" ;
NET "cntrl0_DDR_CAS_N" LOC = "U9" | IOSTANDARD = SSTL2_II ;
NET "cntrl0_DDR_CK[0]" LOC = "V10" ;
NET "cntrl0_DDR_CK[1]" LOC = "V8" ;
NET "cntrl0_DDR_CK_N[0]" LOC = "W10" ;
NET "cntrl0_DDR_CK_N[1]" LOC = "V9" ;
NET "cntrl0_DDR_CKE" LOC = "T6" | IOSTANDARD = SSTL2_II ;
NET "cntrl0_DDR_CS_N" LOC = "T3" | IOSTANDARD = SSTL2_II ;
NET "cntrl0_DDR_DM[0]" LOC = "AF1" ;
NET "cntrl0_DDR_DM[1]" LOC = "AC5" ;
NET "cntrl0_DDR_DM[2]" LOC = "AA3" ;
NET "cntrl0_DDR_DM[3]" LOC = "W8" ;
NET "cntrl0_DDR_DQ[0]" LOC = "AG3" ;
NET "cntrl0_DDR_DQ[10]" LOC = "AC7" ;
NET "cntrl0_DDR_DQ[11]" LOC = "AC6" ;
NET "cntrl0_DDR_DQ[12]" LOC = "AB6" ;
NET "cntrl0_DDR_DQ[13]" LOC = "AC2" ;
NET "cntrl0_DDR_DQ[14]" LOC = "AB4" ;
NET "cntrl0_DDR_DQ[15]" LOC = "AB5" ;
NET "cntrl0_DDR_DQ[16]" LOC = "AA9" ;
NET "cntrl0_DDR_DQ[17]" LOC = "AB8" ;
NET "cntrl0_DDR_DQ[18]" LOC = "AA2" ;
NET "cntrl0_DDR_DQ[19]" LOC = "AA7" ;
NET "cntrl0_DDR_DQ[1]" LOC = "AG4" ;
NET "cntrl0_DDR_DQ[20]" LOC = "Y7" ;
NET "cntrl0_DDR_DQ[21]" LOC = "Y8" ;
NET "cntrl0_DDR_DQ[22]" LOC = "Y5" ;
NET "cntrl0_DDR_DQ[23]" LOC = "Y6" ;
NET "cntrl0_DDR_DQ[24]" LOC = "Y3" ;
NET "cntrl0_DDR_DQ[25]" LOC = "Y4" ;
NET "cntrl0_DDR_DQ[26]" LOC = "Y1" ;
NET "cntrl0_DDR_DQ[27]" LOC = "W9" ;
NET "cntrl0_DDR_DQ[28]" LOC = "W3" ;
NET "cntrl0_DDR_DQ[29]" LOC = "W4" ;
NET "cntrl0_DDR_DQ[2]" LOC = "AG1" ;
NET "cntrl0_DDR_DQ[30]" LOC = "W1" ;
NET "cntrl0_DDR_DQ[31]" LOC = "W2" ;
NET "cntrl0_DDR_DQ[3]" LOC = "AF2" ;
NET "cntrl0_DDR_DQ[4]" LOC = "AE2" ;
NET "cntrl0_DDR_DQ[5]" LOC = "AE3" ;
NET "cntrl0_DDR_DQ[6]" LOC = "AD3" ;
NET "cntrl0_DDR_DQ[7]" LOC = "AD4" ;
NET "cntrl0_DDR_DQ[8]" LOC = "AD1" ;
NET "cntrl0_DDR_DQ[9]" LOC = "AD2" ;
NET "cntrl0_DDR_DQS[0]" LOC = "AE5" ;
NET "cntrl0_DDR_DQS[1]" LOC = "AC3" ;
NET "cntrl0_DDR_DQS[2]" LOC = "Y10" ;
NET "cntrl0_DDR_DQS[3]" LOC = "W6" ;
NET "cntrl0_DDR_RAS_N" LOC = "T4" | IOSTANDARD = SSTL2_II ;
NET "cntrl0_DDR_WE_N" LOC = "T2" | IOSTANDARD = SSTL2_II ;
NET "cntrl0_led_error_output1" LOC = "AA22" | IOSTANDARD = LVCMOS33 ;
NET "cntrl0_rst_dqs_div_in" LOC = "N8" | IOSTANDARD = SSTL2_II ;
NET "cntrl0_rst_dqs_div_out" LOC = "N9" | IOSTANDARD = SSTL2_II ;
NET "reset_in" LOC = "R24" | IOSTANDARD = LVCMOS33 ;
NET "SYS_CLK" LOC = "R21" | IOSTANDARD = LVCMOS33 ;
NET "SYS_CLKb" LOC = "B15" | IOSTANDARD = LVCMOS33 ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
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