write_timingsheet_0.xls

arm控制FPGA的DDR测试代码

Uncertainity parameter                       	Value                                  	Uncertainity before DQS             	Uncertainity after DQS              	Meaning
Tclock                                       	7518.80                               	                                        	                                        	clock period
Tmemory_dll_duty_cycle_dist                  	375.94          	375.94                          	375.94                          	Duty cycle distortion from memory DLL is subtracted from clock phase(equal to halfclock period) to determine Tdata_period
Tdata_period                                 	3383.46                         	                                        	                                        	Data period is half the clock period with 10% duty cycle duty distortion subtracted from it
Data setup time relative to strobe or clock  	500                                  	500                           	0                           	Due to overlap with other parameters only the worstcase value is considered
Data hold time relative to strobe or clock   	500                                  	0                           	500                           	Due to overlap with other parameters only the worstcase value is considered
Tpackage_skew                                	90                               	45                        	45                        	Package skew
Clock jitter                                 	0                                  	0                               	0                               	Same DCM is used to generate DQ and DQS
Clock_tree_skew                              	25                                	25                         	25                         	Small value considered for skew on global clock line since detection of DQS and associated DQ are placed close to each other
Tclock_out_phase                             	140                                	140                         	140                         	Phase offset error between different clock outputs of the same DCM
Pcb_layout_skew                              	20                               	20                        	20                        	Skew between data lines and asociated strobe on the board
Uncertainities                               	1275.00                       	730.00                	730.00                	
Window                                       	1923.46                               	730.00                        	2653.46                        	Valid data window