ddr_cntl_a_s3_ddr_iob.v

arm控制FPGA的DDR测试代码

//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  / Vendor: Xilinx
// \   \   \/ Version: 1.6
//  \   \    Application : MIG
//  /   /    Filename: ddr_cntl_a_s3_ddr_iob.v
// /___/   /\ Date Last Modified:  Tue Jul 11 2006
// \   \  /  \ Date Created: Mon May 2 2005
//  \___\/\___\
// Device: Spartan-3/3e
// Design Name: DDR1_S3/S3e
// Description: This module instantiates DDR IOB output flip-flops, an 
//               output buffer with registered tri-state, and an input buffer  
//               for a single data/dq bit. The DDR IOB output flip-flops 
//               are used to forward data to memory during a write. 
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns/100ps
module ddr_cntl_a_s3_ddr_iob(
      ddr_dq_inout, 
      write_data_falling,
      write_data_rising,
      read_data_in, 
      clk90, 
      write_en_val,
      reset); 



   inout ddr_dq_inout; 
   input write_data_falling;    
   input write_data_rising;    
   input clk90;    	  
   input write_en_val;    
   input reset;
   output read_data_in;   

   parameter GND = 1'b0;
   parameter CLOCK_EN = 1'b1; 

   wire ddr_en;  //Tri-state enable signal
   wire ddr_dq_q;  //Data output intermediate signal
   wire ddr_dq_o;  //Data output intermediate signal
   wire enable_b;

   wire write_data_rising1;
   wire write_data_falling1;

   assign enable_b = ~ write_en_val;
   
   assign #1 write_data_rising1 =  write_data_rising;
   assign #1 write_data_falling1 =  write_data_falling;

   //Transmission data path

   FDDRRSE DDR_OUT
            (.Q  (ddr_dq_q), 
             .C0 (~clk90), 
             .C1 (clk90), 
             .CE (CLOCK_EN),
             .D0 (write_data_rising1), 
             .D1 (write_data_falling1), 
              .R(reset),
               .S(reset)
			);

   FD DQ_T(
             .D   (enable_b),
             .Q   (ddr_en),
             .C   (~clk90));  

 
   OBUFT DQ_OBUFT(
               .I (ddr_dq_q),
               .T (ddr_en),
               .O (ddr_dq_inout));

   //Receive data path

   IBUF DQ_IBUF(
               .I (ddr_dq_inout),
               .O (read_data_in));

endmodule