datasheet.txt

arm控制FPGA的DDR测试代码

                            Datasheet  
Generated by mig version 1.6 
*************   INPUTS GIVEN for MIG 1.6  ***********
 PART                                  :    xc3s4000fg900
 PARTS for compatibility    :     
 Frequency in MHz              :    133
 Speed grade                     :    -4
 No of controllers                :    1
 Synthesis tool                   :    foundation_ise 
 HDL                        :          verilog
 Implementation Options        :                
 DCM used                        :    1        
 ADD TEST BENCH                  :    1         
 Number of write pipelines        :    4         
 Reserved pins:           
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%


**************************************
 Generating interface for controller 0
 Memory type                     :    DDR SDRAM/Components/MT46V16M16P-75 
 Bits per strobe                  :    X8
 Banks for Data          : 7,
 Data bits               : 32
 Banks for addr & cntrl  : 7,
 Row address bits        : 13
 Column address bits     : 9
 Bank address bits       : 2
********************************************
Design parameters : 
       Mode register : 
            Burst Length         : 4(010)
            Burst Type           : sequential(0)
            Cas Latency          : 2(010)
            Operating Mode                 : normal(00000)
       Extended mode register :