ddr_cntl_a_dqs_delay.v

来自「arm控制FPGA的DDR测试代码」· Verilog 代码 · 共 54 行

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  / Vendor: Xilinx
// \   \   \/ Version: 1.6
//  \   \    Application : MIG
//  /   /    Filename: ddr_cntl_a_dqs_delay.v
// /___/   /\ Date Last Modified:  Tue Jul 11 2006
// \   \  /  \ Date Created: Mon May 2 2005
//  \___\/\___\
// Device: Spartan-3/3e
// Design Name: DDR1_S3/S3e
// Description: This module generates the delay in the dqs signal.
///////////////////////////////////////////////////////////////////////////////


`timescale 1ns/100ps
module ddr_cntl_a_dqs_delay( clk_in,
                  sel_in,
                  clk_out);

   input clk_in;
   input [4:0] sel_in;
   output clk_out;

   
   wire delay1;
   wire delay2;     
   wire delay3;
   wire delay4;
   wire delay5;

   parameter HIGH = 1'b1; 


   LUT4 one (.I0(HIGH), .I1(sel_in[4]), .I2(delay5), .I3(clk_in), .O(clk_out));
   defparam one.INIT = 16'hf3c0; 
   LUT4 two (.I0(clk_in), .I1(sel_in[2]), .I2(HIGH), .I3(delay3), .O(delay4));
   defparam two.INIT = 16'hee22; 
   LUT4 three (.I0(clk_in), .I1(sel_in[0]), .I2(delay1), .I3(HIGH), .O(delay2));
   defparam three.INIT = 16'he2e2;
   LUT4 four (.I0(HIGH), .I1(HIGH), .I2(HIGH), .I3(clk_in), .O(delay1));
   defparam four.INIT = 16'hff00;
   LUT4 five (.I0(HIGH), .I1(sel_in[3]), .I2(delay4), .I3(clk_in), .O(delay5));
   defparam five.INIT = 16'hf3c0;  
   LUT4 six (.I0(clk_in), .I1(sel_in[1]), .I2(delay2), .I3(HIGH), .O(delay3));
   defparam six.INIT = 16'he2e2;  

endmodule