ddr_cntl_a_ddr1_dm_0.v

arm控制FPGA的DDR测试代码

//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  / Vendor: Xilinx
// \   \   \/ Version: 1.6
//  \   \    Application : MIG
//  /   /    Filename: ddr_cntl_a_ddr1_dm_0.v
// /___/   /\ Date Last Modified:  Tue Jul 11 2006
// \   \  /  \ Date Created: Mon May 2 2005
//  \___\/\___\
// Device: Spartan-3/3e
// Design Name: DDR1_S3/S3e
// Description: This module instantiates DDR IOB output flip-flops, and an 
//              output buffer for the data mask bits.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns/100ps
`include "../rtl/ddr_cntl_a_parameters_0.v"

module ddr_cntl_a_ddr1_dm_0  (
	           ddr_dm,
	           mask_falling,
	           mask_rising,
	           clk90
                  );
               
   input [(`data_mask_width-1):0]    mask_falling;
   input [(`data_mask_width-1):0]    mask_rising;
   input          clk90;

   output [(`data_mask_width-1):0]   ddr_dm;
   
   wire [(`data_mask_width-1):0]     mask_o;  // Mask output intermediate signal
   wire           gnd;
   wire           vcc;
   
assign gnd = 1'b0;
assign vcc = 1'b1;

// Data Mask Output during a write command

	
FDDRRSE  DDR_DM0_OUT (
                       .Q (mask_o[0]), 
                       .C0(~clk90), 
                       .C1(clk90), 
                       .CE(vcc),
                       .D0(mask_rising[0]), 
                       .D1(mask_falling[0]), 
                       .R (gnd), 
                       .S (gnd)
                      );


FDDRRSE  DDR_DM1_OUT (
                       .Q (mask_o[1]), 
                       .C0(~clk90), 
                       .C1(clk90), 
                       .CE(vcc),
                       .D0(mask_rising[1]), 
                       .D1(mask_falling[1]), 
                       .R (gnd), 
                       .S (gnd)
                      );


FDDRRSE  DDR_DM2_OUT (
                       .Q (mask_o[2]), 
                       .C0(~clk90), 
                       .C1(clk90), 
                       .CE(vcc),
                       .D0(mask_rising[2]), 
                       .D1(mask_falling[2]), 
                       .R (gnd), 
                       .S (gnd)
                      );


FDDRRSE  DDR_DM3_OUT (
                       .Q (mask_o[3]), 
                       .C0(~clk90), 
                       .C1(clk90), 
                       .CE(vcc),
                       .D0(mask_rising[3]), 
                       .D1(mask_falling[3]), 
                       .R (gnd), 
                       .S (gnd)
                      );
            

	
OBUF  DM0_OBUF (
                 .I(mask_o[0]),
                 .O(ddr_dm[0])
                );


OBUF  DM1_OBUF (
                 .I(mask_o[1]),
                 .O(ddr_dm[1])
                );


OBUF  DM2_OBUF (
                 .I(mask_o[2]),
                 .O(ddr_dm[2])
                );


OBUF  DM3_OBUF (
                 .I(mask_o[3]),
                 .O(ddr_dm[3])
                );
                   

endmodule