ddr_cntl_a_cal_ctl_0.v

arm控制FPGA的DDR测试代码

//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  / Vendor: Xilinx
// \   \   \/ Version: 1.6
//  \   \    Application : MIG
//  /   /    Filename: ddr_cntl_a_cal_ctl_0.v
// /___/   /\ Date Last Modified:  Tue Jul 11 2006
// \   \  /  \ Date Created: Mon May 2 2005
//  \___\/\___\
// Device: Spartan-3/3e
// Design Name: DDR1_S3/S3e
// Description: It controlls the calibration circuit
///////////////////////////////////////////////////////////////////////////////

`resetall
`timescale 1ns/100ps
  
`define tap1 5'b01111
`define tap2 5'b10111
`define tap3 5'b11011
`define tap4 5'b11101
`define tap5 5'b11110
`define tap6 5'b11111

`define defaultTap `tap4
  
  module ddr_cntl_a_cal_ctl_0 (flop2,clk,reset,tapForDqs_rl,tapForDqs_tb);
   
   input   	     clk;
   input 	     reset;
   input [31:0]      flop2;
 
   
   output [4:0]      tapForDqs_rl;
  output [4:0]      tapForDqs_tb;
   
   reg [5:0] 	     cnt;  
   reg [5:0] 	     cnt1;  

   reg 		     trans_oneDtct; 
   reg 		     trans_twoDtct; 
   
   reg  [4:0]	     phase_cnt;		

   reg [4:0] 	     tapForDqs_rl;
    reg [4:0] 	     tapForDqs_tb;
   
 

   reg 	[31:0]	tap_dly_reg;	

   reg          enb_trans_two_dtct;
   
   
   
   /***************************** Changed on April 9 For Successive Transition********************/
	always @(posedge clk)	
	begin
	   if(reset)
	      enb_trans_two_dtct <= 1'b0;
 	   else if(phase_cnt >= 5'd3)	
	      enb_trans_two_dtct <= 1'b1;
	   else
	      enb_trans_two_dtct <= 1'b0;		
	end

   /************************************ Changed on April 6 ************************************/

   always @(posedge clk)
   begin
      if(reset)
	     tap_dly_reg <= 32'd0;
      else if(cnt[5] == 1'b1)
	     tap_dly_reg <= flop2;
      else
  	     tap_dly_reg <= tap_dly_reg;
   end
   
   /******************** Free Running Counter For Counting 32 States ****************************/
   
   always @(posedge clk)
     begin
	if(reset || (cnt[5] == 1'b1)) 
	  cnt[5:0] <= 6'b0;
	else
	  cnt[5:0] <= cnt[5:0] + 1'b1;
     end

   always @(posedge clk)
     begin
	if(reset || (cnt1[5] == 1'b1)) 
	  cnt1[5:0] <= 6'b0;
	else
	  cnt1[5:0] <= cnt1[5:0] + 1'b1;
     end
   

  always @(posedge clk)
  begin
     if(reset || (cnt[5] == 1'b1))
     begin
        phase_cnt <= 5'd0;			
     end
     else if (trans_oneDtct & (~trans_twoDtct))
        phase_cnt <= phase_cnt + 1;
     else
        phase_cnt <= phase_cnt;
  end 

   /******************** Checking For The First Transition *************************************/
   always @(posedge clk)
   begin
      if(reset)
	begin
	   trans_oneDtct <= 1'b0;
	   trans_twoDtct <= 1'b0;
	end
	else if(cnt[5] == 1'b1) // cnt is 32
	begin
	   trans_oneDtct <= 1'b0;
	   trans_twoDtct <= 1'b0;
	end
	else if (cnt[4:0] == 5'd0) 
      begin
         if ((tap_dly_reg[0]))
         begin
            trans_oneDtct <= 1'b1;
	      trans_twoDtct <= 1'b0;
         end
      end
	else if ((tap_dly_reg[cnt[4:0]]) & (trans_twoDtct == 1'b0)) 
      begin
       
	      if((trans_oneDtct == 1'b1) && (enb_trans_two_dtct) ) 
            begin	
		   trans_twoDtct <= 1'b1;
	    end
            else 
            begin
		   trans_oneDtct <= 1'b1;
	    end
      end 
   end 
  
always @(posedge clk)
begin
   if(reset)
      tapForDqs_rl <= `defaultTap;
   else if(cnt1[4] && cnt1[3] && cnt1[2] && cnt1[1] && cnt1[0])// Count reached to 32
   begin
      if((trans_oneDtct == 1'b0) || (trans_twoDtct == 1'b0) || (phase_cnt > 5'd11))
         tapForDqs_rl <= `tap4;
      else if((phase_cnt > 5'd8)) 
         tapForDqs_rl <= `tap3;
      else
         tapForDqs_rl <= `tap2;
   end
   else
      tapForDqs_rl <= tapForDqs_rl;
end	


always @ (posedge clk)
begin
	if(reset)
		tapForDqs_tb <= `defaultTap;
	else
	begin
	      if(cnt[4] && cnt[3] && cnt[2] && cnt[1] && cnt[0])
		begin
			if((trans_oneDtct == 1'b0) || (trans_twoDtct == 1'b0) || (phase_cnt > 5'd12))
				tapForDqs_tb<= `tap5;
			else if (phase_cnt < "01000")
					tapForDqs_tb <= `tap1;
		      else if (phase_cnt < "01001")
				tapForDqs_tb <= `tap2;
                  else if (phase_cnt < "01010")
				tapForDqs_tb <= `tap3;
		      else if (phase_cnt < "01100")
				tapForDqs_tb <= `tap4;	
			else	
				tapForDqs_tb <= `tap1;
 		end
		else
		      tapForDqs_tb <= tapForDqs_tb;
 	end		      
end



endmodule