📄 ddr_cntl_a_data_read_controller_0.v
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//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.6
// \ \ Application : MIG
// / / Filename: ddr_cntl_a_data_read_controller_0.v
// /___/ /\ Date Last Modified: Tue Jul 11 2006
// \ \ / \ Date Created: Mon May 2 2005
// \___\/\___\
// Device: Spartan-3/3e
// Design Name: DDR1_S3/S3e
// Description: This module has instantiation for fifo_0_wr_en, fifo_1_wr_en, dqs_delay and wr_gray_cntr.
///////////////////////////////////////////////////////////////////////////////
`include "../rtl/ddr_cntl_a_parameters_0.v"
`timescale 1ns/100ps
module ddr_cntl_a_data_read_controller_0 (
clk90,
reset_r,
reset90_r,
rst_dqs_div_in,
delay_sel,
dqs_int_delay_in0,
dqs_int_delay_in1,
dqs_int_delay_in2,
dqs_int_delay_in3,
fifo_00_wr_en_val,
fifo_01_wr_en_val,
fifo_10_wr_en_val,
fifo_11_wr_en_val,
fifo_20_wr_en_val,
fifo_21_wr_en_val,
fifo_30_wr_en_val,
fifo_31_wr_en_val,
fifo_00_wr_addr_val,
fifo_01_wr_addr_val,
fifo_10_wr_addr_val,
fifo_11_wr_addr_val,
fifo_20_wr_addr_val,
fifo_21_wr_addr_val,
fifo_30_wr_addr_val,
fifo_31_wr_addr_val,
dqs0_delayed_col0_val,
dqs0_delayed_col1_val,
dqs1_delayed_col0_val,
dqs1_delayed_col1_val,
dqs2_delayed_col0_val,
dqs2_delayed_col1_val,
dqs3_delayed_col0_val,
dqs3_delayed_col1_val,
fifo0_rd_addr,
fifo1_rd_addr,
u_data_val,
read_valid_data_1_val
);
input clk90;
input reset_r;
input reset90_r;
input rst_dqs_div_in;
input [4:0] delay_sel;
input dqs_int_delay_in0;
input dqs_int_delay_in1;
input dqs_int_delay_in2;
input dqs_int_delay_in3;
input [3:0] fifo0_rd_addr ;
input [3:0] fifo1_rd_addr ;
output u_data_val;
output read_valid_data_1_val;
output fifo_00_wr_en_val;
output fifo_01_wr_en_val;
output fifo_10_wr_en_val;
output fifo_11_wr_en_val;
output fifo_20_wr_en_val;
output fifo_21_wr_en_val;
output fifo_30_wr_en_val;
output fifo_31_wr_en_val;
output [3:0] fifo_00_wr_addr_val;
output [3:0] fifo_01_wr_addr_val;
output [3:0] fifo_10_wr_addr_val;
output [3:0] fifo_11_wr_addr_val;
output [3:0] fifo_20_wr_addr_val;
output [3:0] fifo_21_wr_addr_val;
output [3:0] fifo_30_wr_addr_val;
output [3:0] fifo_31_wr_addr_val;
output dqs0_delayed_col0_val;
output dqs0_delayed_col1_val;
output dqs1_delayed_col0_val;
output dqs1_delayed_col1_val;
output dqs2_delayed_col0_val;
output dqs2_delayed_col1_val;
output dqs3_delayed_col0_val;
output dqs3_delayed_col1_val;
wire [(`data_strobe_width-1):0] dqs_delayed_col0;
wire [(`data_strobe_width-1):0] dqs_delayed_col1;
wire fifo_00_empty;
wire fifo_01_empty;
wire [3:0] fifo_00_wr_addr;
wire [3:0] fifo_01_wr_addr;
wire [3:0] fifo_10_wr_addr;
wire [3:0] fifo_11_wr_addr;
wire [3:0] fifo_20_wr_addr;
wire [3:0] fifo_21_wr_addr;
wire [3:0] fifo_30_wr_addr;
wire [3:0] fifo_31_wr_addr;
wire read_valid_data_0_1;
reg read_valid_data_r;
reg read_valid_data_r1;
wire dqs0_delayed_col0;
wire dqs0_delayed_col1;
wire dqs1_delayed_col0;
wire dqs1_delayed_col1;
wire dqs2_delayed_col0;
wire dqs2_delayed_col1;
wire dqs3_delayed_col0;
wire dqs3_delayed_col1;
wire fifo_00_wr_en;
wire fifo_01_wr_en;
wire fifo_10_wr_en;
wire fifo_11_wr_en;
wire fifo_20_wr_en;
wire fifo_21_wr_en;
wire fifo_30_wr_en;
wire fifo_31_wr_en;
reg [3:0] fifo_00_wr_addr_d;
reg [3:0] fifo_00_wr_addr_2d;
reg [3:0] fifo_00_wr_addr_3d;
reg [3:0] fifo_01_wr_addr_d;
reg [3:0] fifo_01_wr_addr_2d;
reg [3:0] fifo_01_wr_addr_3d;
wire [(`data_width-1):0] ddr_dq_in;
wire [(`data_width-1):0] write_data270_1;
wire [(`data_width-1):0] write_data270_2;
wire rst_dqs_div;
wire rst_dqs_delay_0_n;
wire rst_dqs_delay_0_n_1;
wire rst_dqs_delay_1_n;
wire rst_dqs_delay_1_n_1;
wire rst_dqs_delay_2_n;
wire rst_dqs_delay_2_n_1;
wire rst_dqs_delay_3_n;
wire rst_dqs_delay_3_n_1;
wire dqs0_delayed_col0_n;
wire dqs0_delayed_col1_n;
wire dqs1_delayed_col0_n;
wire dqs1_delayed_col1_n;
wire dqs2_delayed_col0_n;
wire dqs2_delayed_col1_n;
wire dqs3_delayed_col0_n;
wire dqs3_delayed_col1_n;
reg u_data_val_r;
assign dqs0_delayed_col0 = dqs_delayed_col0[0];
assign dqs0_delayed_col1 = dqs_delayed_col1[0];
assign dqs1_delayed_col0 = dqs_delayed_col0[1];
assign dqs1_delayed_col1 = dqs_delayed_col1[1];
assign dqs2_delayed_col0 = dqs_delayed_col0[2];
assign dqs2_delayed_col1 = dqs_delayed_col1[2];
assign dqs3_delayed_col0 = dqs_delayed_col0[3];
assign dqs3_delayed_col1 = dqs_delayed_col1[3];
assign fifo_00_wr_addr_val = fifo_00_wr_addr;
assign fifo_01_wr_addr_val = fifo_01_wr_addr;
assign fifo_10_wr_addr_val = fifo_10_wr_addr;
assign fifo_11_wr_addr_val = fifo_11_wr_addr;
assign fifo_20_wr_addr_val = fifo_20_wr_addr;
assign fifo_21_wr_addr_val = fifo_21_wr_addr;
assign fifo_30_wr_addr_val = fifo_30_wr_addr;
assign fifo_31_wr_addr_val = fifo_31_wr_addr;
assign fifo_00_wr_en_val = fifo_00_wr_en;
assign fifo_01_wr_en_val = fifo_01_wr_en;
assign fifo_10_wr_en_val = fifo_10_wr_en;
assign fifo_11_wr_en_val = fifo_11_wr_en;
assign fifo_20_wr_en_val = fifo_20_wr_en;
assign fifo_21_wr_en_val = fifo_21_wr_en;
assign fifo_30_wr_en_val = fifo_30_wr_en;
assign fifo_31_wr_en_val = fifo_31_wr_en;
assign dqs0_delayed_col0_val = dqs0_delayed_col0;
assign dqs0_delayed_col1_val = dqs0_delayed_col1;
assign dqs1_delayed_col0_val = dqs1_delayed_col0;
assign dqs1_delayed_col1_val = dqs1_delayed_col1;
assign dqs2_delayed_col0_val = dqs2_delayed_col0;
assign dqs2_delayed_col1_val = dqs2_delayed_col1;
assign dqs3_delayed_col0_val = dqs3_delayed_col0;
assign dqs3_delayed_col1_val = dqs3_delayed_col1;
assign dqs0_delayed_col0_n = ~ dqs0_delayed_col0;
assign dqs0_delayed_col1_n = ~ dqs0_delayed_col1;
assign dqs1_delayed_col0_n = ~ dqs1_delayed_col0;
assign dqs1_delayed_col1_n = ~ dqs1_delayed_col1;
assign dqs2_delayed_col0_n = ~ dqs2_delayed_col0;
assign dqs2_delayed_col1_n = ~ dqs2_delayed_col1;
assign dqs3_delayed_col0_n = ~ dqs3_delayed_col0;
assign dqs3_delayed_col1_n = ~ dqs3_delayed_col1;
assign fifo_00_empty = (fifo0_rd_addr == fifo_00_wr_addr_3d) ? 1'b1 : 1'b0;
assign fifo_01_empty = (fifo1_rd_addr == fifo_01_wr_addr_3d) ? 1'b1 : 1'b0;
assign read_valid_data_0_1 = ((~fifo_00_empty) & (~fifo_01_empty));
assign read_valid_data_1_val = (read_valid_data_0_1);
assign u_data_val = u_data_val_r;
always@(posedge clk90)begin
if(reset90_r)begin
fifo_00_wr_addr_d <= 4'd0;
fifo_01_wr_addr_d <= 4'd0;
fifo_00_wr_addr_2d <= 4'd0;
fifo_01_wr_addr_2d <= 4'd0;
fifo_00_wr_addr_3d <= 4'd0;
fifo_01_wr_addr_3d <= 4'd0;
end
else begin
fifo_00_wr_addr_d <= fifo_00_wr_addr;
fifo_01_wr_addr_d <= fifo_01_wr_addr;
fifo_00_wr_addr_2d <= fifo_00_wr_addr_d;
fifo_01_wr_addr_2d <= fifo_01_wr_addr_d;
fifo_00_wr_addr_3d <= fifo_00_wr_addr_2d;
fifo_01_wr_addr_3d <= fifo_01_wr_addr_2d;
end
end
always@(posedge clk90)begin
if(reset90_r)begin
u_data_val_r <= 1'b0;
read_valid_data_r <= 1'b0;
read_valid_data_r1 <= 1'b0;
end
else begin
read_valid_data_r <= read_valid_data_0_1;
read_valid_data_r1 <= read_valid_data_r;
u_data_val_r <= read_valid_data_r1;
end
end
// rst_dqs_div instantation.
ddr_cntl_a_dqs_delay rst_dqs_div_delayed1 (.clk_in(rst_dqs_div_in), .sel_in(delay_sel), .clk_out(rst_dqs_div));
//DQS Internal Delay Circuit implemented in LUTs
ddr_cntl_a_dqs_delay dqs_delay0_col0(.clk_in(dqs_int_delay_in0), .sel_in(delay_sel),
.clk_out(dqs_delayed_col0[0])) ;
ddr_cntl_a_dqs_delay dqs_delay0_col1(.clk_in(dqs_int_delay_in0), .sel_in(delay_sel),
.clk_out(dqs_delayed_col1[0])) ;
ddr_cntl_a_dqs_delay dqs_delay1_col0(.clk_in(dqs_int_delay_in1), .sel_in(delay_sel),
.clk_out(dqs_delayed_col0[1])) ;
ddr_cntl_a_dqs_delay dqs_delay1_col1(.clk_in(dqs_int_delay_in1), .sel_in(delay_sel),
.clk_out(dqs_delayed_col1[1])) ;
ddr_cntl_a_dqs_delay dqs_delay2_col0(.clk_in(dqs_int_delay_in2), .sel_in(delay_sel),
.clk_out(dqs_delayed_col0[2])) ;
ddr_cntl_a_dqs_delay dqs_delay2_col1(.clk_in(dqs_int_delay_in2), .sel_in(delay_sel),
.clk_out(dqs_delayed_col1[2])) ;
ddr_cntl_a_dqs_delay dqs_delay3_col0(.clk_in(dqs_int_delay_in3), .sel_in(delay_sel),
.clk_out(dqs_delayed_col0[3])) ;
ddr_cntl_a_dqs_delay dqs_delay3_col1(.clk_in(dqs_int_delay_in3), .sel_in(delay_sel),
.clk_out(dqs_delayed_col1[3])) ;
// FIFO write enables
ddr_cntl_a_fifo_0_wr_en_0 fifo_00_wr_en_inst (.clk(dqs0_delayed_col1_n), .reset(reset_r), .din(rst_dqs_div),
.rst_dqs_delay_n(rst_dqs_delay_0_n), .dout(fifo_00_wr_en));
ddr_cntl_a_fifo_1_wr_en_0 fifo_01_wr_en_inst (.clk(dqs0_delayed_col0), .rst_dqs_delay_n(rst_dqs_delay_0_n),
.reset(reset_r), .din(rst_dqs_div), .dout(fifo_01_wr_en));
ddr_cntl_a_fifo_0_wr_en_0 fifo_10_wr_en_inst (.clk(dqs1_delayed_col1_n), .reset(reset_r), .din(rst_dqs_div),
.rst_dqs_delay_n(rst_dqs_delay_1_n), .dout(fifo_10_wr_en));
ddr_cntl_a_fifo_1_wr_en_0 fifo_11_wr_en_inst (.clk(dqs1_delayed_col0), .rst_dqs_delay_n(rst_dqs_delay_1_n),
.reset(reset_r), .din(rst_dqs_div), .dout(fifo_11_wr_en));
ddr_cntl_a_fifo_0_wr_en_0 fifo_20_wr_en_inst (.clk(dqs2_delayed_col1_n), .reset(reset_r), .din(rst_dqs_div),
.rst_dqs_delay_n(rst_dqs_delay_2_n), .dout(fifo_20_wr_en));
ddr_cntl_a_fifo_1_wr_en_0 fifo_21_wr_en_inst (.clk(dqs2_delayed_col0), .rst_dqs_delay_n(rst_dqs_delay_2_n),
.reset(reset_r), .din(rst_dqs_div), .dout(fifo_21_wr_en));
ddr_cntl_a_fifo_0_wr_en_0 fifo_30_wr_en_inst (.clk(dqs3_delayed_col1_n), .reset(reset_r), .din(rst_dqs_div),
.rst_dqs_delay_n(rst_dqs_delay_3_n), .dout(fifo_30_wr_en));
ddr_cntl_a_fifo_1_wr_en_0 fifo_31_wr_en_inst (.clk(dqs3_delayed_col0), .rst_dqs_delay_n(rst_dqs_delay_3_n),
.reset(reset_r), .din(rst_dqs_div), .dout(fifo_31_wr_en));
//write pointer gray counter instances
ddr_cntl_a_wr_gray_cntr fifo_00_wr_addr_inst (.clk(dqs0_delayed_col1), .reset(reset_r),
.cnt_en(fifo_00_wr_en),.wgc_gcnt(fifo_00_wr_addr));
ddr_cntl_a_wr_gray_cntr fifo_01_wr_addr_inst (.clk(dqs0_delayed_col0_n), .reset(reset_r),
.cnt_en(fifo_01_wr_en),.wgc_gcnt(fifo_01_wr_addr));
ddr_cntl_a_wr_gray_cntr fifo_10_wr_addr_inst (.clk(dqs1_delayed_col1), .reset(reset_r),
.cnt_en(fifo_10_wr_en),.wgc_gcnt(fifo_10_wr_addr));
ddr_cntl_a_wr_gray_cntr fifo_11_wr_addr_inst (.clk(dqs1_delayed_col0_n), .reset(reset_r),
.cnt_en(fifo_11_wr_en),.wgc_gcnt(fifo_11_wr_addr));
ddr_cntl_a_wr_gray_cntr fifo_20_wr_addr_inst (.clk(dqs2_delayed_col1), .reset(reset_r),
.cnt_en(fifo_20_wr_en),.wgc_gcnt(fifo_20_wr_addr));
ddr_cntl_a_wr_gray_cntr fifo_21_wr_addr_inst (.clk(dqs2_delayed_col0_n), .reset(reset_r),
.cnt_en(fifo_21_wr_en),.wgc_gcnt(fifo_21_wr_addr));
ddr_cntl_a_wr_gray_cntr fifo_30_wr_addr_inst (.clk(dqs3_delayed_col1), .reset(reset_r),
.cnt_en(fifo_30_wr_en),.wgc_gcnt(fifo_30_wr_addr));
ddr_cntl_a_wr_gray_cntr fifo_31_wr_addr_inst (.clk(dqs3_delayed_col0_n), .reset(reset_r),
.cnt_en(fifo_31_wr_en),.wgc_gcnt(fifo_31_wr_addr));
endmodule
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