ddr_cntl_a_top_0.v

arm控制FPGA的DDR测试代码

//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  / Vendor: Xilinx
// \   \   \/ Version: 1.6
//  \   \    Application : MIG
//  /   /    Filename: ddr_cntl_a_top_0.v
// /___/   /\ Date Last Modified:  Tue Jul 11 2006
// \   \  /  \ Date Created: Mon May 2 2005
//  \___\/\___\
// Device: Spartan-3/3e
// Design Name: DDR1_S3/S3e
// Description: This modules contains the instantiations for
// 			-infrastructure
//			-Iobs
//			-controller
//			-data_paths modules 
///////////////////////////////////////////////////////////////////////////////

`include "../rtl/ddr_cntl_a_parameters_0.v"
  `timescale 1ns/100ps
module    ddr_cntl_a_top_0( 

		
		clk_int,
		clk90_int,
		
		delay_sel_val,
		sys_rst90_val,
		sys_rst180_val,
		sys_rst270_val,
		rst_dqs_div_in,
		rst_dqs_div_out,
		
		 	
		
		user_input_data,       
		user_output_data,      
		user_data_valid,      
		user_input_address,   
		user_config_register,  
		user_command_register, 
		user_cmd_ack,          
		burst_done,            
		init_val,              
		ar_done,               
		DDR_DQS,               
		DDR_DQ,                
		DDR_CKE,               
		DDR_CS_N ,               
		DDR_RAS_N,              
		DDR_CAS_N,              
		DDR_WE_N ,  
		
		DDR_DM,
			
user_data_mask,             

	//user_data_mask,      
		DDR_BA,                
		DDR_A,           
		auto_ref_req,  
		wait_200us, 
		DDR_CK,
		DDR_CK_N,
		sys_rst_val
     );
     
     
 input     rst_dqs_div_in;
 output	  rst_dqs_div_out;
input       clk_int;
input       clk90_int;
input      [4:0] delay_sel_val;
input       sys_rst_val;
input       sys_rst90_val;
input       sys_rst180_val;
input       sys_rst270_val;
input     [((`data_width*2)-1):0]user_input_data;
 output    [((`data_width*2)-1):0]user_output_data;



output    user_data_valid;
  input     [((`row_address + `col_ap_width + `bank_address)-1):0]user_input_address; 
 input     [9:0]user_config_register;
 input     [2:0]user_command_register;
 output    user_cmd_ack;          
input     burst_done;           
 output    init_val;        
output    ar_done;         
inout     [((`data_strobe_width)-1):0]DDR_DQS;
inout     [(`data_width-1):0]DDR_DQ;
output     DDR_CKE;              
output     DDR_CS_N;              
output    auto_ref_req;  
input    wait_200us; 
output     DDR_RAS_N;            
output     DDR_CAS_N;            
output     DDR_WE_N;   

output       [((`data_mask_width)-1):0]  DDR_DM;         

input     [((`data_mask_width*2)-1):0] user_data_mask;          

//input     [((`data_mask_width*2)-1):0] user_data_mask;

output     [`bank_address-1:0]DDR_BA;           
output     [`row_address-1:0]DDR_A;         

output 	[`clk_width-1:0]DDR_CK;
output 	[`clk_width-1:0]DDR_CK_N;



wire rst_calib;     
wire [4:0]delay_sel;
wire sys_rst_val;    
wire sys_rst90_val; 
wire sys_rst180_val; 
wire sys_rst270_val; 
wire clk_int;       
wire clk90_int;     



wire write_enable;      
wire dqs_div_rst;       
wire dqs_enable;        
wire dqs_reset;         


	wire dqs_int_delay_in0; 

	wire dqs_int_delay_in1; 

	wire dqs_int_delay_in2; 

	wire dqs_int_delay_in3; 

wire [(`data_width-1):0]dq; 

wire write_en_val; 
wire reset90_r;    
wire [((`data_mask_width)-1):0] data_mask_f;  
wire [((`data_mask_width)-1):0] data_mask_r;  
wire [(`data_width-1):0]write_data_falling;
wire [(`data_width-1):0]write_data_rising; 



wire ddr_rasb_cntrl; 
wire ddr_casb_cntrl; 
wire ddr_web_cntrl;  

wire [`bank_address-1:0]ddr_ba_cntrl;
wire [`row_address-1:0]ddr_address_cntrl;
wire ddr_cke_cntrl;    
wire ddr_csb_cntrl;    
wire rst_dqs_div_int;  
wire [((`data_mask_width*2)-1):0] user_data_mask;






 ddr_cntl_a_controller_0 controller0  (
				.auto_ref_req      (auto_ref_req), 
				.wait_200us		 (wait_200us), 
				.clk               (clk_int), 
				.rst0              (sys_rst_val),
				.rst180            (sys_rst180_val),
				.address           (user_input_address[(`row_address + `col_ap_width + `bank_address)-1:`bank_address]),
				.bank_address      (user_input_address[`bank_address-1:0]),
				.config_register   (user_config_register),
				.command_register  (user_command_register),
				.burst_done        (burst_done),
				.ddr_rasb_cntrl    (ddr_rasb_cntrl),
				.ddr_casb_cntrl    (ddr_casb_cntrl),
				.ddr_web_cntrl     (ddr_web_cntrl),
				.ddr_ba_cntrl      (ddr_ba_cntrl),
				.ddr_address_cntrl (ddr_address_cntrl),
				.ddr_cke_cntrl     (ddr_cke_cntrl),
				.ddr_csb_cntrl     (ddr_csb_cntrl),
				.dqs_enable        (dqs_enable),
				.dqs_reset         (dqs_reset),
				.write_enable      (write_enable),
				.rst_calib         (rst_calib),
				.rst_dqs_div_int   (rst_dqs_div_int),
				.cmd_ack           (user_cmd_ack),
				.init              (init_val),
				.ar_done           (ar_done)
                                   
                                  );
                             
ddr_cntl_a_data_path_0	data_path0	( 
				.user_input_data    (user_input_data),
				.user_data_mask    (user_data_mask),	
				.clk               (clk_int), 
				.clk90            (clk90_int),
 				.reset              (sys_rst_val),
				.reset90            (sys_rst90_val),
				.reset180           (sys_rst180_val),
				.reset270           (sys_rst270_val),
				.write_enable       (write_enable),
				.rst_dqs_div_in        (dqs_div_rst),
				.delay_sel          (delay_sel),

				
		 .dqs_int_delay_in0  (dqs_int_delay_in0),

		 .dqs_int_delay_in1  (dqs_int_delay_in1),

		 .dqs_int_delay_in2  (dqs_int_delay_in2),

		 .dqs_int_delay_in3  (dqs_int_delay_in3),

				.dq                 (dq),      
				.u_data_val         (user_data_valid),
				.user_output_data   (user_output_data),
				.write_en_val       (write_en_val),
				.reset90_r_val     (reset90_r),
				.data_mask_f        (data_mask_f),
				.data_mask_r        (data_mask_r),
				.write_data_falling (write_data_falling),
				.write_data_rising  (write_data_rising)                     
                                );                           
                          		
							
ddr_cntl_a_infrastructure infrastructure0 
				(
				.sys_rst(sys_rst_val),
				.clk_int(clk_int),
				.rst_calib1(rst_calib),
				.delay_sel_val(delay_sel_val),
				.delay_sel_val1_val(delay_sel)
                                );
ddr_cntl_a_iobs_0	iobs0 
                    (
			.clk               (clk_int), 
			.clk90            (clk90_int), 
		      .ddr_rasb_cntrl    (ddr_rasb_cntrl), 
			.ddr_casb_cntrl    (ddr_casb_cntrl),
			.ddr_web_cntrl     (ddr_web_cntrl),
			.ddr_cke_cntrl     (ddr_cke_cntrl),
			.ddr_csb_cntrl     (ddr_csb_cntrl),
			.ddr_address_cntrl (ddr_address_cntrl),
			.ddr_ba_cntrl      (ddr_ba_cntrl),
			.rst_dqs_div_int   (rst_dqs_div_int),
			.dqs_reset         (dqs_reset),
			.dqs_enable        (dqs_enable),
			.ddr_dqs           (DDR_DQS),
			.ddr_dq            (DDR_DQ),
			.write_data_falling(write_data_falling), 
			.write_data_rising (write_data_rising),
			.write_en_val      (write_en_val),
			.write_en_val1	   (write_en_val),
			.reset90_r        (reset90_r),
			.data_mask_f       (data_mask_f), 
			.data_mask_r       (data_mask_r),
			.DDR_CK		(DDR_CK),
			.DDR_CK_N		(DDR_CK_N),
			.ddr_rasb          (DDR_RAS_N), 
			.ddr_casb          (DDR_CAS_N),
			.ddr_web           (DDR_WE_N),
			.ddr_ba            (DDR_BA),
			.ddr_address       (DDR_A),
			.ddr_cke           (DDR_CKE),
			.ddr_csb           (DDR_CS_N),
			.rst_dqs_div       (dqs_div_rst),
			.rst_dqs_div_in	   (rst_dqs_div_in),
			.rst_dqs_div_out	  ( rst_dqs_div_out),

			
		 .dqs_int_delay_in0  (dqs_int_delay_in0),

		 .dqs_int_delay_in1  (dqs_int_delay_in1),

		 .dqs_int_delay_in2  (dqs_int_delay_in2),

		 .dqs_int_delay_in3  (dqs_int_delay_in3),

						.ddr_dm            (DDR_DM),


			.dq                (dq)

                    );							

endmodule