ddr_cntl_a_rd_gray_cntr.v

arm控制FPGA的DDR测试代码

//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  / Vendor: Xilinx
// \   \   \/ Version: 1.6
//  \   \    Application : MIG
//  /   /    Filename: ddr_cntl_a_rd_gray_cntr.v
// /___/   /\ Date Last Modified:  Tue Jul 11 2006
// \   \  /  \ Date Created: Mon May 2 2005
//  \___\/\___\
// Device: Spartan-3/3e
// Design Name: DDR1_S3/S3e
// Description: 
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns/100ps
module ddr_cntl_a_rd_gray_cntr(	
			clk, 				       
			reset,				
			cnt_en,			                              
			rgc_gcnt );
   input clk;
   input reset;
   input cnt_en;
   output [3:0] rgc_gcnt;


 
wire  [3:0]gc_int ;
reg  [3:0]d_in   ;  



assign    rgc_gcnt = gc_int;

always@(gc_int)
begin
case (gc_int)
4'b0000:  d_in <= 4'b0001;   //1
4'b0001:  d_in <= 4'b0011;   //3
4'b0010:  d_in <= 4'b0110;		//6
4'b0011:  d_in <= 4'b0010;  //2
4'b0100:  d_in <= 4'b1100;  //c
4'b0101:  d_in <= 4'b0100;  //4
4'b0110:  d_in <= 4'b0111;  //7
4'b0111:  d_in <= 4'b0101;  //5
4'b1000:  d_in <= 4'b0000;  //0
4'b1001:  d_in <= 4'b1000;  //8
4'b1010:  d_in <= 4'b1011;  //b
4'b1011:  d_in <= 4'b1001;  //9
4'b1100:  d_in <= 4'b1101;  //d
4'b1101:  d_in <= 4'b1111;  //f
4'b1110:  d_in <= 4'b1010;  //a
4'b1111:  d_in <= 4'b1110;  //e
default : d_in <= 4'b0001;  //1
endcase
end




 FDRE bit0 (
                      .Q( gc_int[0]),
                      .C(clk),
                      .CE(cnt_en),
                      .D(d_in[0]),
		      .R(reset)
                     );

FDRE bit1 (
                      .Q( gc_int[1]),
                      .C(clk),
                      .CE(cnt_en),
                      .D(d_in[1]),
		      .R(reset)
                     );

FDRE bit2 (
                      .Q( gc_int[2]),
                      .C(clk),
                      .CE(cnt_en),
                      .D(d_in[2]),
		      .R(reset)
                     );

FDRE bit3 (
                      .Q( gc_int[3]),
                      .C(clk),
                      .CE(cnt_en),
                      .D(d_in[3]),
		      .R(reset)
                     );



endmodule