ddr_cntl_a_cmd_fsm_0.v

arm控制FPGA的DDR测试代码

//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  / Vendor: Xilinx
// \   \   \/ Version: 1.6
//  \   \    Application : MIG
//  /   /    Filename: ddr_cntl_a_cmd_fsm_0.v
// /___/   /\ Date Last Modified:  Tue Jul 11 2006
// \   \  /  \ Date Created: Mon May 2 2005
//  \___\/\___\
// Device: Spartan-3/3e
// Design Name: DDR1_S3/S3e
// Description: This module generates the commands for the test bench.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns/100ps

module ddr_cntl_a_cmd_fsm_0(
                clk,
                clk90,
	        rst,
	        rst180,
	        rst90,
	        cmd_ack,  
	        cnt_roll,
	        r_w, 
	        refresh_done,  
	        init_val, 
	        u_data_val,  
	        addr_inc,
	        addr_rst,
	        u_cmd,
	        init_counter,
	        lfsr_rst
	              );

   input         clk;               
   input         clk90;
   input         rst;
   input         rst180;
   input         rst90;
   input         cmd_ack;
   input         cnt_roll;   
   output         r_w; 
   input         refresh_done; 
   input         init_val; 
   input         u_data_val;                           
   output        addr_inc;
   output        addr_rst;
   output[2:0]   u_cmd;
   output[6:0]   init_counter;
   output        lfsr_rst;
    
       parameter [3:0] rst_state  = 0,
                       init_start = 1,
		       init       = 2,
		       wr         = 3,
		       rlfsr      = 4,
		       dly        = 5,
		       auto_ref_start = 6,
		       auto_ref   = 7,
		       rd         = 8,
		       wait_state = 9,
		       load_mode_wr = 10,      //A
		       lmd_wait_state = 11;      //B
  
   reg[2:0]    u_cmd;
   reg         addr_inc;
   wire         addr_rst;
   reg[3:0]    next_state;
   reg[3:0]    next_state1;
   reg[3:0]    current_state;
   reg[5:0]    init_dly;
   reg[6:0]    state_bits;
   reg         lfsr_rst_180;
   reg         lfsr_rst_90;
   reg         init_done;
   wire[5:0]   init_dly_p;
   wire        init_chek;
   wire[2:0]   u_cmd_p;
   wire        addr_inc_p;
   wire        lfsr_rst_p;
   wire[3:0]   num_bursts_max;
   wire[4:0]   LMD_WAIT_COUNT_value;
   reg[4:0]    LMD_WAIT_COUNT;
   reg		r_w;
   wire		next_cmd;
   reg		rst_flag;
   reg		temp;

assign lfsr_rst       = lfsr_rst_90;
assign init_counter   = next_state;
assign num_bursts_max = 4'hf;

assign LMD_WAIT_COUNT_value = (next_state == lmd_wait_state) ? 5'b10101 :
                              (LMD_WAIT_COUNT != 5'b00001) ? (LMD_WAIT_COUNT - 5'b00001) :
                               LMD_WAIT_COUNT;

assign u_cmd_p          = (next_state == rd )		? 3'b110 :       // read         	
                        (next_state == wr)		? 3'b100 :       // write        	
                        (next_state == init_start)	? 3'b010 :       // init         	
                        (next_state == auto_ref_start)	? 3'b011 :       // auto_refresh 	
                        (next_state == load_mode_wr)	? 3'b101 :       // load_mode_wr 	
			3'b000;									
          
         
assign addr_inc_p     = ((cmd_ack == 1'b1) && (next_state == wr || next_state == rd));              
                     
assign addr_rst     = rst_flag ;

always@(negedge clk)

begin
  rst_flag <= ( !rst180 && !cmd_ack && !temp);
  temp	   <= ( !rst180 && !cmd_ack);
end
 

assign lfsr_rst_p     =  r_w  ;
                                 
assign init_dly_p     = (next_state == init_start) ? 6'b111111 :
                        (init_dly != 6'b000000) ? init_dly - 1'b1 :
                        6'b000000; 
              
assign init_chek      = init_dly[5] || init_dly[4] || init_dly[3] || init_dly[2] || init_dly[1] || init_dly[0];

assign next_cmd = ((cmd_ack == 1'b0) && next_state == dly);



always @ (negedge clk)
begin
 if(rst180 == 1'b1) 
	r_w <= 1'b0;
 else
    if(cmd_ack == 1'b0 && next_state == rd )
	r_w <= 1'b1;
    else if(cmd_ack == 1'b0 && next_state == wr ) 
        r_w <= 1'b0; 
     else
	r_w <= r_w;
end 


always @ (negedge clk)
begin
  if (rst180 == 1'b1)
    lfsr_rst_180  <= 1'b0;
  else
    lfsr_rst_180  <= lfsr_rst_p;
end

always @ (posedge clk90)
begin
  if (rst90 == 1'b1)
    lfsr_rst_90  <= 1'b0;
  else
    lfsr_rst_90  <= lfsr_rst_180;
end

//for REL6
always @ (negedge clk)
begin
  if (rst180 == 1'b1)
    begin
      u_cmd <= 3'b000;
    end
  else
    begin
      u_cmd <= u_cmd_p;
    end
end

always @ (negedge clk)
begin
  if (rst180 == 1'b1)
    begin
      LMD_WAIT_COUNT <= 5'b0; 
    end
  else
    begin
      LMD_WAIT_COUNT <= LMD_WAIT_COUNT_value;
    end
end

always @ (negedge clk)
begin
  if (rst180 == 1'b1)
     begin
       addr_inc  <= 1'b0;
       init_dly  <= 6'b000000;
     end
    else
     begin
       addr_inc  <= addr_inc_p;
       init_dly  <= init_dly_p;
     end
end

always @ (negedge clk)
begin
   if (rst180 == 1'b1)
       init_done <= 1'b0;
   else
       init_done <= init_val;
end


always @ (next_state or rst180 or cnt_roll or r_w or refresh_done  or init_done or LMD_WAIT_COUNT or next_cmd)
begin
  if (rst180 == 1'b1)
      next_state1 <= rst_state;
  else
    begin
      case (next_state)
         4'b0000 : begin
                     state_bits <= 7'b0000001;   //  01 
                     next_state1 <= init_start;
                   end
         4'b0001 : begin
                      state_bits <= 7'b0000011;   //  03
                      next_state1 <= init;
                   end   
         4'b0010 : begin
                     state_bits <= 7'b0000010;   //  02
                     if (init_done == 1'b1)
                         next_state1 <= wr;
                     else
                         next_state1 <= init;
                   end
          4'b0011 : begin
                     state_bits <= 7'b0000100;   //  04
                     if (cnt_roll == 1'b0)
                        next_state1 <= wr;
                     else
                        next_state1 <= dly;
                    end
          4'b0100 : begin
                     state_bits <= 7'b0001000;   //  08
                     if (r_w == 1'b0)
                         next_state1 <= wr;
                     else if (r_w == 1'b1)
                        next_state1 <= rd;
                    end
          4'b0101 : begin
                     state_bits <= 7'b0010000;   //  10
		       if(next_cmd == 1'b1 && r_w == 1'b0)
		          next_state1 <= rd;
		       else if(next_cmd == 1'b1 && r_w == 1'b1)
		          next_state1 <= wr;
		       else
		          next_state1 <= dly;
                    end

          4'b0110 : begin
                     next_state1 <= auto_ref;           
                    end
          4'b0111 : begin
                     if (refresh_done == 1'b1)
                         next_state1 <= rlfsr;
                     else
                         next_state1 <= auto_ref;
                    end
          4'b1000 : begin
                     state_bits <= 7'b0100000;   //  20
                     if (cnt_roll == 1'b0)
                         next_state1 <= rd;
                     else
                         next_state1 <= dly;                         
                    end
          4'b1011 : begin
                     state_bits <= 7'b1000010;   //  42
                     next_state1 <= wait_state;
                    end
          4'b1001 : begin
                     state_bits <= 7'b1000001;   //  41
                     if(LMD_WAIT_COUNT == 5'b00001)
                         next_state1 <=dly;
                     else   
                        next_state1 <= wait_state;           
                    end
          4'b1010 : begin
                     state_bits <= 7'b1000000;   //  40
                        next_state1 <= dly;           
                    end


          default : begin
                     next_state1 <= rst_state;
                     state_bits <= 7'b0000001;
                    end
      endcase
    end
end


always @ (negedge clk)
begin
  if (rst180 == 1'b1)
   begin
    current_state <= rst_state;
    next_state    <= rst_state;
   end
  else
   begin
    next_state    <= next_state1;
    current_state <= next_state;
   end
end

endmodule