ddr_cntl_a_s3_dqs_iob.v

arm控制FPGA的DDR测试代码

//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  / Vendor: Xilinx
// \   \   \/ Version: 1.6
//  \   \    Application : MIG
//  /   /    Filename: ddr_cntl_a_s3_dqs_iob.v
// /___/   /\ Date Last Modified:  Tue Jul 11 2006
// \   \  /  \ Date Created: Mon May 2 2005
//  \___\/\___\
// Device: Spartan-3/3e
// Design Name: DDR1_S3/S3e
// Description: This module instantiates DDR IOB output flip-flops, an 
//               output buffer with registered tri-state, and an input buffer  
//               for a single strobe/dqs bit. The DDR IOB output flip-flops 
//               are used to forward strobe to memory during a write. During
//               a read, the output of the IBUF is routed to the internal 
//               delay module, dqs_delay. 
///////////////////////////////////////////////////////////////////////////////


`timescale 1ns/100ps
module ddr_cntl_a_s3_dqs_iob(
	           clk,
	           ddr_dqs_reset,
	           ddr_dqs_enable,
	           ddr_dqs,
	           dqs
                   );
               
   input          clk;
   input 	  ddr_dqs_reset; 
   input 	  ddr_dqs_enable;   
   inout          ddr_dqs;
   output         dqs; 

   parameter VCC = 1'b1;
   parameter GND = 1'b0; 
   
   wire           dqs_q;
   wire           ddr_dqs_enable1;
   wire           ddr_dqs_enable_b;
   wire           data1;
   

   assign ddr_dqs_enable_b = ~ddr_dqs_enable;
   assign data1 = (ddr_dqs_reset == 1'b1) ? 1'b0 : 1'b1;
 
 
   FD  U1 ( 
         .D(ddr_dqs_enable_b),
         .Q(ddr_dqs_enable1),
         .C(clk)
         );

   FDDRRSE U2 (  
             .Q(dqs_q),
             .C0(~clk),
             .C1(clk),
             .CE(VCC),
             .D0(GND),
             .D1(data1),
             .R(GND),
             .S(GND)
             );
             
//***********************************************************************
//    IO buffer for dqs signal. Allows for distribution of dqs
//     to the data (DQ) loads.
//***********************************************************************  

   OBUFT  U3  ( 
            .I(dqs_q), 
            .T(ddr_dqs_enable1),
            .O(ddr_dqs)
            );

   IBUF  U4 ( 
                   .I(ddr_dqs),
                   .O(dqs)
                   );

endmodule