ddr_cntl_a_cmp_data_0.v

arm控制FPGA的DDR测试代码

/////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  / Vendor: Xilinx
// \   \   \/ Version: 1.6
//  \   \    Application : MIG
//  /   /    Filename: ddr_cntl_a_cmp_data_0.v
// /___/   /\ Date Last Modified:  Tue Jul 11 2006 
// \   \  /  \ Date Created: Mon May 2 2005
//  \___\/\___\
//Device: Spartan-3/3e
//Design Name: DDR1_S3/S3e
//Description: This module generates the error signal in case of bit errors.
//                  It compares the read data witht the write data. 
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns/100ps
`include "../rtl/ddr_cntl_a_parameters_0.v"

module    ddr_cntl_a_cmp_data_0(    
     clk,            
     data_valid,     
     lfsr_data,      
     read_data,      
     rst,            
     led_error_output, 
     data_valid_out 
     );

input  clk;
input  data_valid;
input  [((`data_width*2)-1):0]lfsr_data; 
input  [((`data_width*2)-1):0]read_data;
input  rst;
output led_error_output;
output data_valid_out;




reg  led_state;     
reg valid;
wire error;
   reg[((`data_width/8)-1):0]      byte_err;
   reg[((`data_width/8)-1):0]      byte_err1;
   reg           val_reg;
   reg[((`data_width*2)-1):0]    read_data_reg;
      
   
   wire[15:0]    lfsr_0;

   wire[15:0]    lfsr_1;

   wire[15:0]    lfsr_2;

   wire[15:0]    lfsr_3;


   
   wire[15:0]    data_0;

   wire[15:0]    data_1;

   wire[15:0]    data_2;

   wire[15:0]    data_3;



always @ (posedge clk)
begin
  if (rst == 1'b1)
    read_data_reg <= 'd0;
  else
    read_data_reg <= read_data;
end

always @ (posedge clk)
begin
  if (rst == 1'b1)
    begin

      valid   <= 1'b0;
    end
  else
    begin

      valid   <= data_valid;
    end
end
assign data_valid_out = valid;



	assign data_0         = read_data_reg[15:0];

	assign data_1         = read_data_reg[31:16];

	assign data_2         = read_data_reg[47:32];

	assign data_3         = read_data_reg[63:48];




	assign lfsr_0         = lfsr_data[15:0];

	assign lfsr_1         = lfsr_data[31:16];

	assign lfsr_2         = lfsr_data[47:32];

	assign lfsr_3         = lfsr_data[63:48];


always @ (posedge clk)
begin
   if (rst == 1'b1)
     begin
        byte_err <=  'd0;
	byte_err1 <= 'd0;
	val_reg <= 1'b0;
     end
   else
     begin
	val_reg <= valid;

	
	byte_err[0] <= (data_0[7:0] != lfsr_0[7:0]);
	byte_err1[0] <= (data_0[15:8] != lfsr_0[15:8]);

	byte_err[1] <= (data_1[7:0] != lfsr_1[7:0]);
	byte_err1[1] <= (data_1[15:8] != lfsr_1[15:8]);

	byte_err[2] <= (data_2[7:0] != lfsr_2[7:0]);
	byte_err1[2] <= (data_2[15:8] != lfsr_2[15:8]);

	byte_err[3] <= (data_3[7:0] != lfsr_3[7:0]);
	byte_err1[3] <= (data_3[15:8] != lfsr_3[15:8]);

     end
end 
   
   assign error = ((|(byte_err[((`data_width/8)-1):0])) || (|(byte_err1[((`data_width/8)-1):0]))) && val_reg;

always @ (posedge clk)
begin
  led_state <= ( !rst  && ( error || led_state));
end 


always @ (posedge clk)
begin
    if (error == 1'b1)
	$display($time, " ### LED_ERROR : byte_err= %b , byte_err1= %b ###",byte_err,byte_err1);
end 
   

assign led_error_output = (led_state == 1'b1) ? 1'b1 : 1'b0;
              


endmodule