📄 ddr_cntl_a_data_read_0.v
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//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.6
// \ \ Application : MIG
// / / Filename: ddr_cntl_a_data_read_0.v
// /___/ /\ Date Last Modified: Tue Jul 11 2006
// \ \ / \ Date Created: Mon May 2 2005
// \___\/\___\
// Device: Spartan-3/3e
// Design Name: DDR1_S3/S3e
// Description: Data read operation performed through RAM8D in this module.
///////////////////////////////////////////////////////////////////////////////
`include "../rtl/ddr_cntl_a_parameters_0.v"
`timescale 1ns/100ps
module ddr_cntl_a_data_read_0
(clk90,
reset90_r,
ddr_dq_in,
read_valid_data_1,
fifo_00_wr_en,
fifo_01_wr_en,
fifo_10_wr_en,
fifo_11_wr_en,
fifo_20_wr_en,
fifo_21_wr_en,
fifo_30_wr_en,
fifo_31_wr_en,
fifo_00_wr_addr,
fifo_01_wr_addr,
fifo_10_wr_addr,
fifo_11_wr_addr,
fifo_20_wr_addr,
fifo_21_wr_addr,
fifo_30_wr_addr,
fifo_31_wr_addr,
dqs0_delayed_col0,
dqs0_delayed_col1,
dqs1_delayed_col0,
dqs1_delayed_col1,
dqs2_delayed_col0,
dqs2_delayed_col1,
dqs3_delayed_col0,
dqs3_delayed_col1,
user_output_data,
fifo0_rd_addr_val,
fifo1_rd_addr_val);
input clk90;
input reset90_r;
input [(`data_width-1):0] ddr_dq_in;
input read_valid_data_1;
input fifo_00_wr_en;
input fifo_01_wr_en;
input fifo_10_wr_en;
input fifo_11_wr_en;
input fifo_20_wr_en;
input fifo_21_wr_en;
input fifo_30_wr_en;
input fifo_31_wr_en;
input [3:0] fifo_00_wr_addr;
input [3:0] fifo_01_wr_addr;
input [3:0] fifo_10_wr_addr;
input [3:0] fifo_11_wr_addr;
input [3:0] fifo_20_wr_addr;
input [3:0] fifo_21_wr_addr;
input [3:0] fifo_30_wr_addr;
input [3:0] fifo_31_wr_addr;
input dqs0_delayed_col0;
input dqs0_delayed_col1;
input dqs1_delayed_col0;
input dqs1_delayed_col1;
input dqs2_delayed_col0;
input dqs2_delayed_col1;
input dqs3_delayed_col0;
input dqs3_delayed_col1;
output [((`data_width*2)-1):0] user_output_data;
output [3:0] fifo0_rd_addr_val;
output [3:0] fifo1_rd_addr_val;
reg read_valid_data_1_r;
reg read_valid_data_1_r1;
reg read_valid_data_1_r2;
reg [3:0] fifo00_rd_addr_r;
reg [3:0] fifo01_rd_addr_r;
reg [3:0] fifo10_rd_addr_r;
reg [3:0] fifo11_rd_addr_r;
reg [3:0] fifo20_rd_addr_r;
reg [3:0] fifo21_rd_addr_r;
reg [3:0] fifo30_rd_addr_r;
reg [3:0] fifo31_rd_addr_r;
reg [3:0] fifop_rd_addr_r;
reg [`DatabitsPerReadClock-1:0] fifo_00_data_out_r;
reg [`DatabitsPerReadClock-1:0] fifo_01_data_out_r;
reg [`DatabitsPerReadClock-1:0] fifo_10_data_out_r;
reg [`DatabitsPerReadClock-1:0] fifo_11_data_out_r;
reg [`DatabitsPerReadClock-1:0] fifo_20_data_out_r;
reg [`DatabitsPerReadClock-1:0] fifo_21_data_out_r;
reg [`DatabitsPerReadClock-1:0] fifo_30_data_out_r;
reg [`DatabitsPerReadClock-1:0] fifo_31_data_out_r;
reg [((`data_width*2)-1):0] first_sdr_data;
wire [3:0] fifo00_rd_addr;
wire [3:0] fifo01_rd_addr;
wire [`DatabitsPerReadClock-1:0] fifo_00_data_out;
wire [`DatabitsPerReadClock-1:0] fifo_01_data_out;
wire [`DatabitsPerReadClock-1:0] fifo_10_data_out;
wire [`DatabitsPerReadClock-1:0] fifo_11_data_out;
wire [`DatabitsPerReadClock-1:0] fifo_20_data_out;
wire [`DatabitsPerReadClock-1:0] fifo_21_data_out;
wire [`DatabitsPerReadClock-1:0] fifo_30_data_out;
wire [`DatabitsPerReadClock-1:0] fifo_31_data_out;
wire dqs0_delayed_col0_n;
wire dqs0_delayed_col1_n;
wire dqs1_delayed_col0_n;
wire dqs1_delayed_col1_n;
wire dqs2_delayed_col0_n;
wire dqs2_delayed_col1_n;
wire dqs3_delayed_col0_n;
wire dqs3_delayed_col1_n;
assign dqs0_delayed_col0_n = ~ dqs0_delayed_col0;
assign dqs0_delayed_col1_n = ~ dqs0_delayed_col1;
assign dqs1_delayed_col0_n = ~ dqs1_delayed_col0;
assign dqs1_delayed_col1_n = ~ dqs1_delayed_col1;
assign dqs2_delayed_col0_n = ~ dqs2_delayed_col0;
assign dqs2_delayed_col1_n = ~ dqs2_delayed_col1;
assign dqs3_delayed_col0_n = ~ dqs3_delayed_col0;
assign dqs3_delayed_col1_n = ~ dqs3_delayed_col1;
assign user_output_data = first_sdr_data;
assign fifo0_rd_addr_val = fifo01_rd_addr;
assign fifo1_rd_addr_val = fifo00_rd_addr;
always@(posedge clk90)begin
if(reset90_r)begin
fifo_00_data_out_r <= `DatabitsPerReadClock'd0;
fifo_01_data_out_r <= `DatabitsPerReadClock'd0;
end
else
begin
fifo_00_data_out_r <= fifo_00_data_out;
fifo_01_data_out_r <= fifo_01_data_out;
end
end
always@(posedge clk90)begin
if(reset90_r)begin
fifo_10_data_out_r <= `DatabitsPerReadClock'd0;
fifo_11_data_out_r <= `DatabitsPerReadClock'd0;
end
else
begin
fifo_10_data_out_r <= fifo_10_data_out;
fifo_11_data_out_r <= fifo_11_data_out;
end
end
always@(posedge clk90)begin
if(reset90_r)begin
fifo_20_data_out_r <= `DatabitsPerReadClock'd0;
fifo_21_data_out_r <= `DatabitsPerReadClock'd0;
end
else
begin
fifo_20_data_out_r <= fifo_20_data_out;
fifo_21_data_out_r <= fifo_21_data_out;
end
end
always@(posedge clk90)begin
if(reset90_r)begin
fifo_30_data_out_r <= `DatabitsPerReadClock'd0;
fifo_31_data_out_r <= `DatabitsPerReadClock'd0;
end
else
begin
fifo_30_data_out_r <= fifo_30_data_out;
fifo_31_data_out_r <= fifo_31_data_out;
end
end
always@(posedge clk90)begin
if(reset90_r)begin
fifo01_rd_addr_r <= 4'd0;
fifo00_rd_addr_r <= 4'd0;
end
else begin
fifo00_rd_addr_r <= fifo00_rd_addr;
fifo01_rd_addr_r <= fifo01_rd_addr;
end
end
always@(posedge clk90)begin
if(reset90_r)begin
fifo11_rd_addr_r <= 4'd0;
fifo10_rd_addr_r <= 4'd0;
end
else begin
fifo10_rd_addr_r <= fifo00_rd_addr;
fifo11_rd_addr_r <= fifo01_rd_addr;
end
end
always@(posedge clk90)begin
if(reset90_r)begin
fifo21_rd_addr_r <= 4'd0;
fifo20_rd_addr_r <= 4'd0;
end
else begin
fifo20_rd_addr_r <= fifo00_rd_addr;
fifo21_rd_addr_r <= fifo01_rd_addr;
end
end
always@(posedge clk90)begin
if(reset90_r)begin
fifo31_rd_addr_r <= 4'd0;
fifo30_rd_addr_r <= 4'd0;
end
else begin
fifo30_rd_addr_r <= fifo00_rd_addr;
fifo31_rd_addr_r <= fifo01_rd_addr;
end
end
always@(posedge clk90)begin
if(reset90_r)begin
first_sdr_data <= 144'd0;
read_valid_data_1_r <= 1'b0;
read_valid_data_1_r1 <= 1'b0;
read_valid_data_1_r2 <= 1'b0;
end
else begin
read_valid_data_1_r <= read_valid_data_1;
read_valid_data_1_r1 <= read_valid_data_1_r;
read_valid_data_1_r2 <= read_valid_data_1_r1;
if(read_valid_data_1_r1)begin
first_sdr_data <= {
fifo_30_data_out_r,
fifo_20_data_out_r,
fifo_10_data_out_r,
fifo_00_data_out_r,
fifo_31_data_out_r,
fifo_21_data_out_r,
fifo_11_data_out_r,
fifo_01_data_out_r
};
end
end
end
// rd address gray counters
ddr_cntl_a_rd_gray_cntr fifo0_rd_addr_inst (.clk(clk90), .reset(reset90_r), .cnt_en(read_valid_data_1),
.rgc_gcnt(fifo00_rd_addr));
ddr_cntl_a_rd_gray_cntr fifo1_rd_addr_inst (.clk(clk90), .reset(reset90_r), .cnt_en(read_valid_data_1),
.rgc_gcnt(fifo01_rd_addr));
// 16X1 fifo instantations
ddr_cntl_a_RAM8D_0 strobe0 ( .DOUT(fifo_00_data_out[`DatabitsPerReadClock-1:0]),
.WADDR(fifo_00_wr_addr[3:0]),
.DIN(ddr_dq_in[7:0]), .RADDR(fifo00_rd_addr_r[3:0]),
.WCLK0(dqs0_delayed_col0), .WCLK1(dqs0_delayed_col1),
.WE(fifo_00_wr_en) );
ddr_cntl_a_RAM8D_0 strobe0_n ( .DOUT(fifo_01_data_out[`DatabitsPerReadClock-1:0]),
.WADDR(fifo_01_wr_addr[3:0]),
.DIN(ddr_dq_in[7:0]), .RADDR(fifo01_rd_addr_r[3:0]),
.WCLK0(dqs0_delayed_col0_n), .WCLK1(dqs0_delayed_col1_n),
.WE(fifo_01_wr_en) );
ddr_cntl_a_RAM8D_0 strobe1 ( .DOUT(fifo_10_data_out[`DatabitsPerReadClock-1:0]),
.WADDR(fifo_10_wr_addr[3:0]),
.DIN(ddr_dq_in[15:8]), .RADDR(fifo10_rd_addr_r[3:0]),
.WCLK0(dqs1_delayed_col0), .WCLK1(dqs1_delayed_col1),
.WE(fifo_10_wr_en) );
ddr_cntl_a_RAM8D_0 strobe1_n ( .DOUT(fifo_11_data_out[`DatabitsPerReadClock-1:0]),
.WADDR(fifo_11_wr_addr[3:0]),
.DIN(ddr_dq_in[15:8]), .RADDR(fifo11_rd_addr_r[3:0]),
.WCLK0(dqs1_delayed_col0_n), .WCLK1(dqs1_delayed_col1_n),
.WE(fifo_11_wr_en) );
ddr_cntl_a_RAM8D_0 strobe2 ( .DOUT(fifo_20_data_out[`DatabitsPerReadClock-1:0]),
.WADDR(fifo_20_wr_addr[3:0]),
.DIN(ddr_dq_in[23:16]), .RADDR(fifo20_rd_addr_r[3:0]),
.WCLK0(dqs2_delayed_col0), .WCLK1(dqs2_delayed_col1),
.WE(fifo_20_wr_en) );
ddr_cntl_a_RAM8D_0 strobe2_n ( .DOUT(fifo_21_data_out[`DatabitsPerReadClock-1:0]),
.WADDR(fifo_21_wr_addr[3:0]),
.DIN(ddr_dq_in[23:16]), .RADDR(fifo21_rd_addr_r[3:0]),
.WCLK0(dqs2_delayed_col0_n), .WCLK1(dqs2_delayed_col1_n),
.WE(fifo_21_wr_en) );
ddr_cntl_a_RAM8D_0 strobe3 ( .DOUT(fifo_30_data_out[`DatabitsPerReadClock-1:0]),
.WADDR(fifo_30_wr_addr[3:0]),
.DIN(ddr_dq_in[31:24]), .RADDR(fifo30_rd_addr_r[3:0]),
.WCLK0(dqs3_delayed_col0), .WCLK1(dqs3_delayed_col1),
.WE(fifo_30_wr_en) );
ddr_cntl_a_RAM8D_0 strobe3_n ( .DOUT(fifo_31_data_out[`DatabitsPerReadClock-1:0]),
.WADDR(fifo_31_wr_addr[3:0]),
.DIN(ddr_dq_in[31:24]), .RADDR(fifo31_rd_addr_r[3:0]),
.WCLK0(dqs3_delayed_col0_n), .WCLK1(dqs3_delayed_col1_n),
.WE(fifo_31_wr_en) );
endmodule
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