ddr_cntl_a_controller_0.v

arm控制FPGA的DDR测试代码

                            else
                                 next_state1 <= WRITE_WAIT;
                         end
                       default :
                         next_state1 <= WRITE_WAIT;
                     endcase
                     end
          BURST_WRITE :
                       begin
              if ((burst_length == 3'b001) && (wrburst_end == 1'b0))   //Added for BL =2
                        next_state1 <= BURST_WRITE;
             else if ((burst_length == 3'b001) && (wrburst_end == 1'b1))
				next_state1 <= PRECHARGE_AFTER_WRITE;  
               else
                         next_state1 <= WRITE_WAIT;
                       end
          READ_AFTER_WRITE :
                     next_state1 <= BURST_READ;
          PRECHARGE_AFTER_WRITE :
                     next_state1 <= PRECHARGE_AFTER_WRITE_2;
          PRECHARGE_AFTER_WRITE_2 : 
          		begin  
                     if(WR_COUNT == 2'd0)   
		       precharge_flag <= 1'b1;
		     else
                     next_state1 <= PRECHARGE_AFTER_WRITE_2;
                     end   
                    

          READ_WAIT : begin
                     case(rdburst_end)
                     1'b1 :
                      next_state1 <= PRECHARGE_AFTER_WRITE;
                     1'b0 :
                         begin
                           if (CAS_COUNT == 3'b001) //For BL = 8
                             next_state1 <= BURST_READ;
                         else
                             next_state1 <= READ_WAIT;
                         end
                     default :
                         next_state1 <= READ_WAIT;
                    endcase
                     end
          BURST_READ :
                     begin
              if ((burst_length == 3'b001) && (rdburst_end == 1'b0))    //Added for BL =2
                        next_state1 <= BURST_READ;
             else if ((burst_length == 3'b001) && (rdburst_end == 1'b1))
				next_state1 <= PRECHARGE_AFTER_WRITE;  
               else
                         next_state1 <= READ_WAIT;
                     end
          BURST_STOP :
                    next_state1 <= READ_WAIT;
          default :
                next_state1 <= IDLE;
    endcase
  end
end

//************************************************************************************************
// address generation logic
//************************************************************************************************

assign address_config[`row_address-1:7] = (INIT_COUNT == 3'b010) ? {`row_address-7{1'b0}} :
                                          (INIT_COUNT == 3'b011) ? {{`row_address-9{1'b0}},2'b10}:
                                          (next_state == PRECHARGE) ? 8 :
                                          {`row_address-7{1'b0}};

assign address_config[6:4] =  (INIT_COUNT == 3'b010) ? 3'b000 :
                              (next_state == LOAD_MODE_REG) ? cas_latency :
                              3'b000;
                              
assign address_config[3] = 1'b0; // design uses sequential burst

assign address_config[2:0] =  (INIT_COUNT == 3'b010) ? 3'b000 :
                              (next_state == LOAD_MODE_REG) ? burst_length :
                              3'b000;


assign ddr_address1 = (next_state == LOAD_MODE_REG || next_state == PRECHARGE) ? address_config :
                      (next_state == ACTIVE) ? row_address_reg :
                        ((next_state == BURST_WRITE) || (next_state == FIRST_WRITE) || (next_state == BURST_READ)) ? column_address_reg : 
                      `row_address'b0;
                      
assign ddr_ba1 =  ((next_state == LOAD_MODE_REG) && (INIT_COUNT == 3'b010)) ? {{`bank_address-1{1'b0}},1'b1} :
                  ((next_state == ACTIVE) || (next_state == FIRST_WRITE) || (next_state == BURST_WRITE) || (next_state == BURST_READ)) ? BA_address_reg :
                  {{`bank_address-1{1'b0}},1'b0};



//********************************************************************************************************
//  register row address
//********************************************************************************************************
always @ (negedge clk)       //(posedge clk180)
begin
  if (rst180_r == 1'b1)
     row_address_active_reg <= `row_address'b0;
  else
   begin
     if (next_state == ACTIVE)
         row_address_active_reg <= row_address_reg;
     else
         row_address_active_reg <= row_address_active_reg;
   end
end

always @ (negedge clk)       //(posedge clk180)
begin
  if (rst180_r == 1'b1)
     row_address_conflict <= 1'b0;
  else
   begin
     if (row_address_reg != row_address_active_reg)
         row_address_conflict <= 1'b1;
     else
         row_address_conflict <= 1'b0;
   end
end

//********************************************************************************************************
//  register bank address
//********************************************************************************************************

always @ (negedge clk)       //(posedge clk180)
begin
  if (rst180_r == 1'b1)
      BA_address_active <= `bank_address'b0;
  else
    begin
      if (next_state == ACTIVE)
          BA_address_active <= BA_address_reg;
      else
          BA_address_active <= BA_address_active;
    end
end

always @ (negedge clk)       //(posedge clk180)
begin
  if (rst180_r == 1'b1)
      BA_address_conflict <= 1'b0;
  else
    begin
      if (BA_address_reg != BA_address_active)
          BA_address_conflict <= 1'b1;
      else
          BA_address_conflict <= 1'b0;
    end
end

//********************************************************************************************************
//  register column address
//********************************************************************************************************
always @ (negedge clk)       //(posedge clk180)
begin
  if (rst180_r == 1'b1)
    begin
     column_address_reg1 <= `row_address'b0;
     column_address_reg2 <= `row_address'b0;
     column_address_reg3 <= `row_address'b0;
     column_address_reg4 <= `row_address'b0;
     column_address_reg5 <= `row_address'b0;
     column_address_reg6 <= `row_address'b0; 

    end
  else
    begin
     column_address_reg1 <= column_address_reg;
     column_address_reg2 <= column_address_reg1;
     column_address_reg3 <= column_address_reg2;
     column_address_reg4 <= column_address_reg3;
     column_address_reg5 <= column_address_reg4;
     column_address_reg6 <= column_address_reg5;
    end
end



//**************************************************************************************************
//Pipeline stages for ddr_address and ddr_ba
//**************************************************************************************************

always @ (negedge clk)       //(posedge clk180)
begin
if (rst180_r == 1'b1)
  begin
   ddr_address2  <= `row_address'b0;
   ddr_address3  <= `row_address'b0;
   ddr_ba2       <= `bank_address'b0;
   ddr_ba3       <= `bank_address'b0;
  end
else
  begin
    ddr_address2 <= ddr_address1;
    ddr_address3 <= ddr_address2;
    ddr_ba2      <= ddr_ba1;
    ddr_ba3      <= ddr_ba2;
  end
end

always @ (negedge clk)       //(posedge clk180)
begin
  if (rst180_r == 1'b1)
    begin
      ddr_address4  <= `row_address'b0;
      ddr_address5  <= `row_address'b0;
      ddr_address_cntrl   <= `row_address'b0;
    end
  else
    begin
      ddr_address4  <= ddr_address3;
      ddr_address5  <= ddr_address4;
     ddr_address_cntrl   <= ddr_address1;
    end
end

always @ (negedge clk)       //(posedge clk180)
begin
  if (rst180_r == 1'b1)
    begin
     ddr_ba4 <= `bank_address'b0;
     ddr_ba5 <= `bank_address'b0;
     ddr_ba_cntrl  <= `bank_address'b0;
    end
  else
    begin
     ddr_ba4 <= ddr_ba3;
     ddr_ba5 <= ddr_ba4;
     ddr_ba_cntrl  <= ddr_ba1;

    end
end

//************************************************************************************************
// control signals to the Memory
//************************************************************************************************

assign ddr_rasb1 = ((next_state == ACTIVE) || (next_state == PRECHARGE) || (next_state == AUTO_REFRESH) || (next_state == LOAD_MODE_REG)) ? 1'b0 : 1'b1;

assign ddr_casb1 = ((next_state == BURST_READ) || (next_state == BURST_WRITE) || (next_state == FIRST_WRITE) || 
                   (next_state == AUTO_REFRESH) || (next_state == LOAD_MODE_REG)) ? 1'b0 : 1'b1;

assign ddr_web1  = ((next_state == BURST_WRITE) || (next_state == FIRST_WRITE) || (next_state == BURST_STOP) || 
                   (next_state == PRECHARGE) || (next_state == LOAD_MODE_REG)) ? 1'b0 : 1'b1;


//*************************************************************************************************
// register CONTROL SIGNALS outputs
//**************************************************************************************************
always @ (negedge clk)       //(posedge clk180)
begin
  if (rst180_r == 1'b1)
    begin
      ddr_rasb3 <= 1'b1;
      ddr_casb3 <= 1'b1;
      ddr_web3  <= 1'b1;
      ddr_rasb2 <= 1'b1;
      ddr_casb2 <= 1'b1;
      ddr_web2  <= 1'b1;
    end
  else
    begin
      ddr_rasb2    <= ddr_rasb1;
      ddr_casb2    <= ddr_casb1;
      ddr_web2     <= ddr_web1;
      ddr_rasb3     <= ddr_rasb2;
      ddr_casb3    <= ddr_casb2;
      ddr_web3     <= ddr_web2;
    end
end

always @ (negedge clk)       //(posedge clk180)
begin
  if (rst180_r == 1'b1)
    begin
      ddr_rasb4  <= 1'b1;
      ddr_casb4  <= 1'b1;
      ddr_web4   <= 1'b1; 
      ddr_rst_dqs_rasb4  <= 1'b1;
      ddr_rst_dqs_casb4  <= 1'b1;
      ddr_rst_dqs_web4   <= 1'b1; 
      ddr_rasb5 <= 1'b1;
      ddr_casb5 <= 1'b1;
      ddr_web5  <= 1'b1;
    end
  else
    begin
      ddr_rasb4  <= ddr_rasb3;
      ddr_casb4  <= ddr_casb3;
      ddr_web4   <= ddr_web3;
      ddr_rasb5   <= ddr_rasb4;
      ddr_casb5   <= ddr_casb4;
      ddr_web5    <= ddr_web4;
    
	 if(cas_latency == 3'b011) // --CL3
	 begin
		ddr_rst_dqs_rasb4  <= ddr_rasb1;
   		ddr_rst_dqs_casb4  <= ddr_casb1;
   		ddr_rst_dqs_web4   <= ddr_web1; 
	 end
	 
	else
	begin
	  ddr_rst_dqs_rasb4  <= ddr_rst_dqs_rasb4;
   	ddr_rst_dqs_casb4  <= ddr_rst_dqs_casb4;
   	ddr_rst_dqs_web4   <= ddr_rst_dqs_web4; 
	end
	end
end

always @ (negedge clk)       //(posedge clk180)
begin
    if (rst180_r == 1'b1)
        dqs_div_cascount <= 3'b000;
    else
      begin
  if( (ddr_rasb1 == 1'b1) && (ddr_casb1 == 1'b0) && (ddr_web1 == 1'b1) && ((cas_latency == 3'b010)||(cas_latency == 3'b110)) )  // For CL= 2,2.5 & BL=8,4
          dqs_div_cascount <= burst_cnt_max ; // Modified by Abhishake for BL=8

   else if((ddr_rst_dqs_rasb4 == 1'b1) && (ddr_rst_dqs_casb4 == 1'b0) && (ddr_rst_dqs_web4 == 1'b1)) // For BL = 4,8 & CL=3
             dqs_div_cascount <= burst_cnt_max ;
   else
    begin
     if (dqs_div_cascount != 3'b000)
        dqs_div_cascount <= dqs_div_cascount - 1'b1;
      else
       dqs_div_cascount <= dqs_div_cascount;
       end
  end
end

always @ (negedge clk)       //(posedge clk180)
begin
    if (rst180_r == 1'b1)
        dqs_div_rdburstcount <= 3'b000;
    else
      begin
             if (dqs_div_cascount == 3'b001  && burst_length == 3'b010)
            dqs_div_rdburstcount <= 3'b010; 
        else if (dqs_div_cascount == 3'b011  && burst_length == 3'b011)
            dqs_div_rdburstcount <= 3'b100; 
        else if (dqs_div_cascount == 3'b001  && burst_length == 3'b001) // Added for BL = 2
            dqs_div_rdburstcount <= 3'b001;                             // Added for BL = 2  

        else 
          begin
            if (dqs_div_rdburstcount != 3'b000)
               dqs_div_rdburstcount <= dqs_div_rdburstcount - 1'b1;
            else
               dqs_div_rdburstcount <= dqs_div_rdburstcount;
          end
      end
end


always @ (negedge clk)       //(posedge clk180)
begin
    if (rst180_r == 1'b1)
        rst_dqs_div_r <= 1'b0;
    else
      begin
        if (dqs_div_cascount == 3'b001  && burst_length == 3'b010)
            rst_dqs_div_r <= 1'b1;
        else if (dqs_div_cascount == 3'b011  && burst_length == 3'b011)
            rst_dqs_div_r <= 1'b1;
	  else if (dqs_div_cascount == 3'b001  && burst_length == 3'b001)   // Added for BL = 2
            rst_dqs_div_r <= 1'b1;                                         // Added for BL = 2 

        else if (dqs_div_rdburstcount == 3'b001 && dqs_div_cascount == 3'b000)
            rst_dqs_div_r <= 1'b0;
        else
            rst_dqs_div_r <= rst_dqs_div_r;
      end
end



//For BL=2,4,8 n Comp or Unbuffered Dimms
assign rst_dqs_div_r1 = rst_dqs_div_r;

always @(negedge clk)    //(posedge clk180)
begin
  if (rst180_r == 1'b1)
    dly_dqs_div_r <= 1'b0;
  else
    dly_dqs_div_r <= rst_dqs_div_r;
end


 FD  rst_calib0  (
                 .Q(rst_calib),     
                 
                 
   .D(rst_dqs_div_r),  

		                                              
                 .C(~clk)     //.C(clk180)
                 );         
        
FD  rst_iob_out (
                 .Q(rst_dqs_div_int),     
                 
       	     
   .D(rst_dqs_div_r1),  

	           
		     
		     
   .C(clk)  

       	     
	           
		     	
                 );
   
                 
endmodule