📄 ddr_cntl_a_controller_0.v
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begin
DQS_enable1 <= 1'b0;
DQS_enable2 <= 1'b0;
DQS_enable3 <= 1'b0;
DQS_enable4 <= 1'b0;
DQS_reset1_clk0 <= 1'b0;
DQS_reset2_clk0 <= 1'b0;
DQS_reset3_clk0 <= 1'b0;
DQS_reset4_clk0 <= 1'b0;
end
else
begin
DQS_enable1 <= DQS_enable_int;
DQS_enable2 <= DQS_enable1;
DQS_enable3 <= DQS_enable2;
DQS_enable4 <= DQS_enable3;
DQS_reset1_clk0 <= DQS_reset_int;
DQS_reset2_clk0 <= DQS_reset1_clk0;
DQS_reset3_clk0 <= DQS_reset2_clk0;
DQS_reset4_clk0 <= DQS_reset3_clk0;
end
end
//****************************************************************************************************
//Generating WRITE and READ enable signals
//*****************************************************************************************************
assign write_enable_out = ((wrburst_chk == 1'b1) || (wrburst_end_cnt != 3'b000)) ? 1'b1 : 1'b0;
assign read_enable_out = ((CAS_COUNT != 3'b000) || (rdburst_chk == 1'b1)) ? 1'b1 : 1'b0; //BL=8
assign read_enable_out_r = read_enable_out || rdburst_end_r;
always @(negedge clk) //(posedge clk180)
begin
if (rst180_r == 1'b1)
write_enable <= 1'b0;
else
write_enable <= write_enable_out;
end
assign cmd_ack = ack_reg;
FD ACK_REG_INST1 (
.Q(ack_reg),
.D(ack_o),
.C(~clk) //.C(clk180)
);
assign ack_o = ((write_cmd_in == 1'b1) || (write_cmd1 == 1'b1) || (read_cmd1 == 1'b1)); //Sarala, June22
assign read_write_state = ((next_state1 == FIRST_WRITE) || (next_state1 == BURST_WRITE) || (next_state1 == BURST_READ)) ? 1'b1 : 1'b0;
//*********************************************************************************************
// to initialize memory
//*********************************************************************************************
always @ (negedge clk) //(posedge clk180)
begin
if (rst180_r == 1'b1)
begin
init_memory <= 1'b0;
INIT_DONE <= 1'b0;
end
else
begin
init_memory <= init_mem;
INIT_DONE <= init_done_value && ~INIT_DONE || INIT_DONE;
end
end
assign init_mem = (initialize_memory == 1'b1) ? 1'b1 :
((INIT_COUNT == 3'b111) && (mrdCnt0 == 1'b1)) ? 1'b0 :
init_memory;
// counter for Memory Initialization sequence
assign INIT_COUNT_value = ((precharge_flag || ldMdReg_flag || aref_flag)) ? (INIT_COUNT + 1'b1) :
INIT_COUNT;
assign init_done_value = ((INIT_COUNT == 3'b111) && (DLL_RST_COUNT == 8'b0000_0001)) ? 1'b1 : 1'b0;
//Counter for DLL Reset complete
assign DLL_RST_COUNT_value = (INIT_COUNT == 3'b010) ? 'd200 : //200
(DLL_RST_COUNT != 8'b0000_0001)? (DLL_RST_COUNT - 8'b0000_0001):
8'b0000_0001;
//Signal to go directly to ACTIVE state instead of LMR state after Write/Read cmd_in from user
assign GO_TO_ACTIVE_value =( ((write_cmd_in == 1'b1) && (write_cmd1 != 1'b1))|| ((read_cmd == 1'b1) && (read_cmd1 != 1'b1)) )? 1'b1 : 1'b0;
// To check if there is a bank conflict after an ACTIVE command has been issued for a particular bank
assign CONFLICT_value = ((RRD_COUNT == 2'b01) && (BA_address_conflict == 1'b1)) ? 1'b1 : 1'b0;
always @ (negedge clk) //(posedge clk180)
begin
if (rst180_r == 1'b1)
begin
CONFLICT <= 1'b0;
GO_TO_ACTIVE <= 1'b0;
end
else
begin
CONFLICT <= CONFLICT_value;
GO_TO_ACTIVE <= GO_TO_ACTIVE_value;
end
end
//**********************************************************************************************
// Register counter values
//**********************************************************************************************
always @ (negedge clk) //(posedge clk180)
begin
if (rst180_r == 1'b1)
begin
INIT_COUNT <= 3'b000;
DLL_RST_COUNT <= 8'b0000_0000;
RP_COUNT <= 3'b000;
rpCnt0 <= 1'b1;
rpCnt1 <= 1'b0;
mrdCnt0 <= 1'b1;
mrdCnt1 <= 1'b0;
rcdrCnt0 <= 1'b1;
rcdrCnt1 <= 1'b0;
rcdwCnt0 <= 1'b1;
rcdwCnt1 <= 1'b0;
rcCnt0 <= 1'b1;
MRD_COUNT <= 2'b00;
RFC_COUNT <= 5'b00000;
RAS_COUNT <= 4'b0000;
CAS_COUNT <= 3'b000; //BL = 8
RRD_COUNT <= 2'b00;
RCDR_COUNT <= 3'b000;
RCDW_COUNT <= 2'b00;
RC_COUNT <= 4'b0000;
RDBURST_END_CNT <= 3'b000;
wrburst_end_cnt <= 3'b000;
WR_COUNT <= 2'b00;
RFC_COUNT_reg <= 1'b0;
AR_Done_reg <= 1'b0;
end
else
begin
INIT_COUNT <= init_memory ? INIT_COUNT_value : INIT_COUNT;
DLL_RST_COUNT <= DLL_RST_COUNT_value;
RP_COUNT <= rp_cnt_value;
MRD_COUNT <= MRD_COUNT_value;
RFC_COUNT <= RFC_COUNT_value;
RAS_COUNT <= ras_count_value;
CAS_COUNT <= cas_count_value;
RRD_COUNT <= RRD_COUNT_value;
RCDR_COUNT <= RCDR_COUNT_value;
RCDW_COUNT <= RCDW_COUNT_value;
RC_COUNT <= RC_COUNT_value;
wrburst_end_cnt <= wrburst_end_cnt_value;
RDBURST_END_CNT <= rdburst_end_cnt_value;
WR_COUNT <= WR_COUNT_value;
mrdCnt0 <= (MRD_COUNT[1] == 1'b0 && MRD_COUNT_value[1:0] != 2'b11);
mrdCnt1 <= (MRD_COUNT == 2'b10);
rpCnt0 <= (RP_COUNT[2] == 1'b0 && RP_COUNT[1] == 1'b0 && !rp_cnt_value[2]);
rpCnt1 <= (RP_COUNT == 3'b010);
rcdrCnt0 <= (RCDR_COUNT[2] == 1'b0 && RCDR_COUNT[1] == 1'b0 && !RCDR_COUNT_value[2]);
rcdrCnt1 <= (RCDR_COUNT == 3'b010);
rcdwCnt0 <= (RCDW_COUNT[1] == 1'b0 && RCDW_COUNT_value[1:0] != 2'b11 );
rcdwCnt1 <= (RCDW_COUNT == 2'b10);
rcCnt0 <= (RC_COUNT[3] == 1'b0 && RC_COUNT[2] == 1'b0 && RC_COUNT[1] == 1'b0 && RC_COUNT_value[3:2] != 2'b11);
if(RFC_COUNT == 5'b00010 ) //2
AR_Done_reg <= 1'b1;
else
AR_Done_reg <= 1'b0;
if(AR_Done_reg == 1'b1)
RFC_COUNT_reg <= 1'b1;
else if (Auto_Ref_issued_p == 1'b1)
RFC_COUNT_reg <= 1'b0;
else
RFC_COUNT_reg <= RFC_COUNT_reg;
end
end
//*********************************************************************************************
// to check current state for the address bus
//*********************************************************************************************
always @ (negedge clk) //(posedge clk180)
begin
if (rst180_r == 1'b1)
begin
next_state <= IDLE;
end
else
begin
if (precharge_flag)
begin
next_state <= PRECHARGE;
end
else if (ldMdReg_flag)
begin
next_state <= LOAD_MODE_REG;
end
else if (aref_flag)
begin
next_state <= AUTO_REFRESH;
end
else if (idle_flag)
begin
next_state <= IDLE;
end
else
begin
next_state <= next_state1;
end
end
end
//*********************************************************************************************
// main state machine
//*********************************************************************************************
always @ (next_state or rst180_r or init_memory or RP_COUNT or INIT_COUNT or MRD_COUNT or RFC_COUNT or PRECHARGE_CMD
or CONFLICT or RCDW_COUNT or write_cmd or RCDR_COUNT or read_rcd_end or burst_length or
wrburst_end or wrburst_end_cnt or rdburst_end or CAS_COUNT or WR_COUNT or GO_TO_ACTIVE or ld_mode or
auto_ref or RFC_COUNT_reg or write_cmd3 or read_cmd5 or rpCnt0 or rpCnt1 or mrdCnt0 or mrdCnt1
or rcdrCnt1 or rcdwCnt1)
begin
if (rst180_r == 1'b1)
begin
next_state1 <= IDLE;
precharge_flag <= 1'b0;
ldMdReg_flag <= 1'b0;
aref_flag <= 1'b0;
idle_flag <= 1'b0;
end
else
begin
next_state1 <= IDLE;
precharge_flag <= 1'b0;
ldMdReg_flag <= 1'b0;
aref_flag <= 1'b0;
idle_flag <= 1'b0;
case (next_state)
IDLE : begin
if (init_memory == 1'b1)
begin
case (INIT_COUNT)
3'b000 :
begin
precharge_flag <= 1'b1;
end
3'b001 :
begin
if (rpCnt1 == 1'b1)
begin
ldMdReg_flag <= 1'b1;
end
else
begin
idle_flag <= 1'b1;
end
end
3'b010 :
begin
if (mrdCnt1 == 1'b1)
begin
ldMdReg_flag <= 1'b1;
end
else
begin
idle_flag <= 1'b1;
end
end
3'b011 :
begin
if (mrdCnt1 == 1'b1)
begin
precharge_flag <= 1'b1;
end
else
begin
idle_flag <= 1'b1;
end
end
3'b100 :
begin
if (rpCnt1 == 1'b1)
begin
aref_flag <= 1'b1;
end
else
begin
idle_flag <= 1'b1;
end
end
3'b101 :
begin
if (RFC_COUNT_reg == 1'b1)
begin
aref_flag <= 1'b1;
end
else
begin
idle_flag <= 1'b1;
end
end
3'b110 :
begin
if (RFC_COUNT_reg == 1'b1)
begin
ldMdReg_flag <= 1'b1;
end
else
begin
idle_flag <= 1'b1;
end
end
3'b111 :
begin
if (mrdCnt0 != 1'b1)
begin
idle_flag <= 1'b1;
end
else
next_state1 <=next_state ;
end
default :
idle_flag <= 1'b1;
endcase
end
else if ( auto_ref == 1'b1 && RFC_COUNT_reg == 1'b1 && rpCnt0 == 1'b1)
aref_flag <= 1'b1;
else if (PRECHARGE_CMD == 1'b1)
precharge_flag <= 1'b1;
else if (ld_mode == 1'b1)
ldMdReg_flag <= 1'b1;
else if (GO_TO_ACTIVE == 1'b1 || CONFLICT == 1'b1)
next_state1 <= ACTIVE;
else
idle_flag <= 1'b1;
end
PRECHARGE :
idle_flag <= 1'b1;
LOAD_MODE_REG :
idle_flag <= 1'b1;
AUTO_REFRESH :
idle_flag <= 1'b1;
ACTIVE :
next_state1 <= ACTIVE_WAIT;
ACTIVE_WAIT :
begin
if ((rcdwCnt1 == 1'b1) && (write_cmd3 == 1'b1))
next_state1 <= FIRST_WRITE;
else if ((rcdrCnt1 == 1'b1) && (read_cmd5 == 1'b1))
next_state1 <= BURST_READ;
else
next_state1 <= ACTIVE_WAIT;
end
FIRST_WRITE :
begin
if ((burst_length == 3'b001) && (wrburst_end == 1'b0)) //Added for BL = 2
next_state1 <= BURST_WRITE;
else if ((burst_length == 3'b001) && (wrburst_end == 1'b1))
next_state1 <= PRECHARGE_AFTER_WRITE;
else
next_state1 <= WRITE_WAIT;
end
WRITE_WAIT :
begin
case(wrburst_end)
1'b1 :
next_state1 <= PRECHARGE_AFTER_WRITE;
1'b0 :
begin
if (wrburst_end_cnt == 3'b001) // (wrburst_end_cnt == 3'b001)
next_state1 <= BURST_WRITE;
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